Patents by Inventor Georg Meyer-Berg

Georg Meyer-Berg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200395334
    Abstract: Disclosed is a method that includes: providing semiconductor dies, each of the semiconductor dies having a thinner active region surrounded by a thicker inactive region so that each of the semiconductor dies has a first cavity vertically aligned with the thinner active region and laterally surrounded by the thicker inactive region; providing a metal carrier having connection parts secured to the metal carrier, each of the connection parts dimensioned to fit within the first cavity of one of the semiconductor dies; inserting each of the connection parts of the metal carrier into the respective first cavity of the corresponding semiconductor die; after the inserting, attaching the metal carrier to the semiconductor dies; and after the attaching, singulating the metal carrier so that each of the connection parts of the metal carrier remains attached to the corresponding semiconductor die.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Joachim Mahler, Michael Bauer, Christoph Liebl, Georg Meyer-Berg, Georg Reuther, Peter Strobel
  • Patent number: 10854547
    Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 1, 2020
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg, Guenter Tutsch
  • Publication number: 20200266166
    Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Christoph Kutter, Ewald Soutschek, Georg Meyer-Berg
  • Patent number: 10734352
    Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Irmgard Escher-Poeppel, Khalil Hosseini, Johannes Lodermeyer, Joachim Mahler, Thorsten Meyer, Georg Meyer-Berg, Ivan Nikitin, Reinhard Pufall, Edmund Riedl, Klaus Schmidt, Manfred Schneegans, Patrick Schwarz
  • Patent number: 10679959
    Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Intel Deutschland GmbH
    Inventors: Christoph Kutter, Ewald Soutschek, Georg Meyer-Berg
  • Patent number: 10600690
    Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Claus von Waechter, Michael Bauer, Holger Doepke, Dominic Maier, Daniel Porwol, Tobias Schmidt
  • Patent number: 10529678
    Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: January 7, 2020
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Christoph Kutter, Ewald Soutschek, Georg Meyer-Berg
  • Patent number: 10522447
    Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Infineon Technologies AG
    Inventor: Georg Meyer-Berg
  • Publication number: 20190287907
    Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 19, 2019
    Applicant: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg, Guenter Tutsch
  • Publication number: 20190221521
    Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 18, 2019
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier, Georg Meyer-Berg
  • Patent number: 10297564
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg
  • Publication number: 20190123009
    Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 25, 2019
    Inventors: Christoph Kutter, Ewald Soutschek, Georg Meyer-Berg
  • Publication number: 20190109112
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: Joachim Mahler, Georg Meyer-Berg
  • Publication number: 20190103378
    Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Inventors: Irmgard Escher-Poeppel, Khalil Hosseini, Johannes Lodermeyer, Joachim Mahler, Thorsten Meyer, Georg Meyer-Berg, Ivan Nikitin, Reinhard Pufall, Edmund Riedl, Klaus Schmidt, Manfred Schneegans, Patrick Schwarz
  • Patent number: 10211158
    Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier, Georg Meyer-Berg
  • Patent number: 10177112
    Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Edward Fuergut, Georg Meyer-Berg
  • Publication number: 20180350683
    Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 6, 2018
    Inventors: Georg Meyer-Berg, Claus von Waechter, Michael Bauer, Holger Doepke, Dominic Maier, Daniel Porwol, Tobias Schmidt
  • Patent number: 10121690
    Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Edward Fuergut, Joachim Mahler
  • Patent number: 10090216
    Abstract: A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Reinhard Pufall, Michael Goroll, Rainer Dudek
  • Patent number: 10056295
    Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate. A layer of a permanent adhesive is applied onto a surface of the carrier. A structured intermediate layer is provided. The applied permanent adhesive bonds the carrier to the product substrate. The structured intermediate layer is arranged between the product substrate and the carrier. A surface of the structured intermediate layer and a surface of the permanent adhesive are in direct contact to a surface of the product substrate. The structured intermediate layer decreases a bonding strength between the product substrate and the carrier.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: August 21, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Claus von Waechter, Michael Bauer, Holger Doepke, Dominic Maier, Daniel Porwol, Tobias Schmidt