Patents by Inventor Georg PARTEDER
Georg PARTEDER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11764109Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.Type: GrantFiled: April 3, 2019Date of Patent: September 19, 2023Assignee: AMS AGInventors: Jochen Kraft, Georg Parteder, Stefan Jessenig, Franz Schrank, Jörg Siegert
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Publication number: 20220352016Abstract: A method is proposed of producing a semiconductor body with a trench. The semiconductor body comprises a substrate. The method comprising the step of etching the trench into the substrate using an etching mask. An oxide layer is formed at least on a sidewall of the trench by oxidation of the substrate. A passivation layer is formed on the oxide layer and the bottom of the trench. The passivation layer is removed from the bottom of the trench. Finally, a metallization layer is deposited into the trench.Type: ApplicationFiled: October 23, 2020Publication date: November 3, 2022Inventors: Georg PARTEDER, Thomas BODNER
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Publication number: 20220328380Abstract: An open through-substrate via, TSV, comprises an insulation layer disposed adjacent to at least a portion of side walls of a trench and to a surface of a substrate body. The TSV further comprises a metallization layer disposed adjacent to at least a portion of the insulation layer and to at least a portion of a bottom wall of said trench, a redistribution layer disposed adjacent to at least a portion of the metallization layer and a portion of the insulation layer disposed adjacent to the surface, and a capping layer disposed adjacent to at least a portion of the metallization layer and to at least a portion of the redistribution layer. The insulation layer and/or the capping layer comprise sublayers that are distinct from each other in terms of material properties. A first of the sublayers is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface and a second of the sublayers is disposed adjacent to at least a portion of the surface.Type: ApplicationFiled: August 27, 2020Publication date: October 13, 2022Inventors: Georg PARTEDER, Jochen KRAFT, Stefan JESSENIG
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Patent number: 11404352Abstract: A dielectric layer is arranged on a main surface of a semiconductor substrate, a metal layer providing a contact area is embedded in the dielectric layer, a top metal is arranged on an opposite main surface of the substrate, and an electrically conductive interconnection through the substrate, which comprises a plurality of metallizations arranged in a plurality of via holes, connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer penetrating the substrate.Type: GrantFiled: February 15, 2019Date of Patent: August 2, 2022Assignee: AMSAGInventors: Victor Sidorov, Stefan Jessenig, Georg Parteder
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Patent number: 11367672Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.Type: GrantFiled: March 20, 2019Date of Patent: June 21, 2022Assignee: AMS AGInventors: Jochen Kraft, Georg Parteder, Anderson Pires Singulani, Raffaele Coppeta, Franz Schrank
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Patent number: 11355386Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided.Type: GrantFiled: August 23, 2018Date of Patent: June 7, 2022Assignee: AMS AGInventors: Georg Parteder, Jochen Kraft, Raffaele Coppeta
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Publication number: 20210366764Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided.Type: ApplicationFiled: August 23, 2018Publication date: November 25, 2021Inventors: Georg Parteder, Jochen Kraft, Raffaele Coppeta
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Patent number: 11127656Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via.Type: GrantFiled: February 14, 2018Date of Patent: September 21, 2021Assignee: AMS AGInventors: Jochen Kraft, Georg Parteder, Anderson Singulani, Raffaele Coppeta, Franz Schrank
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Publication number: 20210175153Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.Type: ApplicationFiled: March 20, 2019Publication date: June 10, 2021Inventors: Jochen KRAFT, Georg PARTEDER, Anderson PIRES SINGULANI, Raffaele COPPETA, Franz SCHRANK
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Publication number: 20210020511Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.Type: ApplicationFiled: April 3, 2019Publication date: January 21, 2021Inventors: Jochen Kraft, Georg Parteder, Stefan Jessenig, Franz Schrank, Jörg Siegert
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Publication number: 20210005534Abstract: A dielectric layer is arranged on a main surface of a semiconductor substrate, a metal layer providing a contact area is embedded in the dielectric layer, a top metal is arranged on an opposite main surface of the substrate, and an electrically conductive interconnection through the substrate, which comprises a plurality of metallizations arranged in a plurality of via holes, connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer penetrating the substrate.Type: ApplicationFiled: February 15, 2019Publication date: January 7, 2021Inventors: Victor Sidorov, Stefan Jessenig, Georg Parteder
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Publication number: 20200020611Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via.Type: ApplicationFiled: February 14, 2018Publication date: January 16, 2020Inventors: Jochen Kraft, Georg Parteder, Anderson Singulani, Raffaele Coppeta, FRANZ SCHRANK
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Patent number: 10243017Abstract: The sensor chip stack comprises a sensor substrate of a semiconductor material including a sensor, a chip fastened to the sensor substrate, the chip including an integrated circuit, electric interconnections between the sensor substrate and the chip, electric terminals of the chip, the chip being arranged between the electric terminals and the sensor substrate, and a molding material arranged adjacent to the chip, the electric terminals of the chip being free from the molding material.Type: GrantFiled: June 28, 2017Date of Patent: March 26, 2019Assignee: ams International AGInventors: Georg Parteder, Jochen Kraft, Franz Schrank, Thomas Troxler, Andreas Fitzi
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Publication number: 20180158992Abstract: The invention relates to a method for producing an LED module (1) and comprises at least the following steps:—providing at least one LED chip (4) on a substrate material (2), and—dispensing a not-cured (flowable/liquid) potting compound (3) on top of the LED chip (4), said potting compound (3) containing at least one type of luminescent particles and preferably a matrix material. During the step of dispensing, a predetermined potential is applied directly or indirectly to at least one LED chip (4).Type: ApplicationFiled: May 20, 2016Publication date: June 7, 2018Applicant: TRIDONIC JENNERSDORF GMBHInventors: Robert HÖBER-NEUHOLD, Clemens MAYER, Peter PACHLER, Georg PARTEDER, Florian WIMMER
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Publication number: 20180006074Abstract: The sensor chip stack comprises a sensor substrate of a semiconductor material including a sensor, a chip fastened to the sensor substrate, the chip including an integrated circuit, electric interconnections between the sensor substrate and the chip, electric terminals of the chip, the chip being arranged between the electric terminals and the sensor substrate, and a molding material arranged adjacent to the chip, the electric terminals of the chip being free from the molding material.Type: ApplicationFiled: June 28, 2017Publication date: January 4, 2018Inventors: Georg PARTEDER, Jochen KRAFT, Franz SCHRANK, Thomas TROXLER, Andreas FITZI