Abstract: A semiconductor device includes a substrate—with a rear surface and a main surface, an intermetal dielectric on the main surface of substrate, a metal layer embedded in the intermetal dielectric. The metal layer includes a top barrier layer. The top barrier layer is at a side of the metal layer facing away from the substrate. The semiconductor device also includes a through-substrate-via (TSV) reaching from the rear surface of the substrate to the top barrier layer of the metal layer. The TSV includes a metallization configured to electrically contact the metal layer from the rear surface of the substrate. The TSV includes a via hole. The via hole penetrates the substrate and the intermetal dielectric between the substrate and the metal layer. The via hole further penetrates the metal layer up to the top barrier layer.

Abstract: A method is proposed of producing a semiconductor body with a trench. The semiconductor body comprises a substrate. The method comprising the step of etching the trench into the substrate using an etching mask. An oxide layer is formed at least on a sidewall of the trench by oxidation of the substrate. A passivation layer is formed on the oxide layer and the bottom of the trench. The passivation layer is removed from the bottom of the trench. Finally, a metallization layer is deposited into the trench.

Abstract: An open through-substrate via, TSV, comprises an insulation layer disposed adjacent to at least a portion of side walls of a trench and to a surface of a substrate body. The TSV further comprises a metallization layer disposed adjacent to at least a portion of the insulation layer and to at least a portion of a bottom wall of said trench, a redistribution layer disposed adjacent to at least a portion of the metallization layer and a portion of the insulation layer disposed adjacent to the surface, and a capping layer disposed adjacent to at least a portion of the metallization layer and to at least a portion of the redistribution layer. The insulation layer and/or the capping layer comprise sublayers that are distinct from each other in terms of material properties. A first of the sublayers is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface and a second of the sublayers is disposed adjacent to at least a portion of the surface.

Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.

Abstract: The invention relates to a method for producing an LED module (1) and comprises at least the following steps:—providing at least one LED chip (4) on a substrate material (2), and—dispensing a not-cured (flowable/liquid) potting compound (3) on top of the LED chip (4), said potting compound (3) containing at least one type of luminescent particles and preferably a matrix material. During the step of dispensing, a predetermined potential is applied directly or indirectly to at least one LED chip (4).

Abstract: The sensor chip stack comprises a sensor substrate of a semiconductor material including a sensor, a chip fastened to the sensor substrate, the chip including an integrated circuit, electric interconnections between the sensor substrate and the chip, electric terminals of the chip, the chip being arranged between the electric terminals and the sensor substrate, and a molding material arranged adjacent to the chip, the electric terminals of the chip being free from the molding material.