Abstract: The particle sensor device comprises a substrate, a photodetector, a dielectric on or above the substrate, a source of electromagnetic radiation, and a through-substrate via in the substrate. The through-substrate via is exposed to the environment, in particular to ambient air. A waveguide is arranged in or above the dielectric so that the electromagnetic radiation emitted by the source of electromagnetic radiation is coupled into a portion of the waveguide. A further portion of the waveguide is opposite the photodetector, so that said portions of the waveguide are on different sides of the through-substrate via, and the waveguide traverses the through-substrate via.

Abstract: A semiconductor body comprises a buried layer of a first type of conductivity, a first region of the first type of conductivity, a shallow region of a second type of conductivity at a first surface of the semiconductor body, a sinker of the first type of conductivity located at the first surface of the semiconductor body, and a separating region of the first type of conductivity encircling at least one of the sinker and the buried layer. The first region is between the buried layer and the shallow region.

Abstract: The SPAD device comprises a single-photon avalanche diode and a further single-photon avalanche diode having breakdown voltages, the single-photon avalanche diodes being integrated in the same device. The breakdown voltages are equal or differ by less than 10%. The single-photon avalanche diode is configured to enable to induce triggering or to have a dark count rate that is higher than the dark count rate of the further single-photon avalanche diode.

Abstract: A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.

Abstract: The semiconductor device comprises a bipolar transistor with emitter, base and collector, a current or voltage source electrically connected with the emitter, and a quenching component electrically connected with the collector, the bipolar transistor being configured for operation at a collector-to-base voltage above the breakdown voltage.

Abstract: A avalanche diode arrangement comprises an avalanche diode (11) that is coupled to a first voltage terminal (14) and to a first node (15), a latch comparator (12) with a first input (16) coupled to the first node (15), a second input (17) for receiving a reference voltage (VREF) and an enable input (21) for receiving a comparator enable signal (CLK), and a quenching circuit (13) coupled to the first node (15).

Abstract: A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.

Abstract: The particle sensor device comprises a substrate, a photodetector, a dielectric on or above the substrate, a source of electromagnetic radiation, and a through-substrate via in the substrate. The through-substrate via is exposed to the environment, in particular to ambient air. A waveguide is arranged in or above the dielectric so that the electromagnetic radiation emitted by the source of electromagnetic radiation is coupled into a portion of the waveguide. A further portion of the waveguide is opposite the photodetector, so that said portions of the waveguide are on different sides of the through-substrate via, and the waveguide traverses the through-substrate via.

Abstract: The semiconductor device comprises a bipolar transistor with emitter, base and collector, a current or voltage source electrically connected with the emitter, and a quenching component electrically connected with the collector, the bipolar transistor being configured for operation at a collector-to-base voltage above the breakdown voltage.

Abstract: A avalanche diode arrangement comprises an avalanche diode (11) that is coupled to a first voltage terminal (14) and to a first node (15), a latch comparator (12) with a first input (16) coupled to the first node (15), a second input (17) for receiving a reference voltage (VREF) and an enable input (21) for receiving a comparator enable signal (CLK), and a quenching circuit (13) coupled to the first node (15).

Abstract: The SPAD device comprises a single-photon avalanche diode and a further single-photon avalanche diode having breakdown voltages, the single-photon avalanche diodes being integrated in the same device. The breakdown voltages are equal or differ by less than 10%. The single-photon avalanche diode is configured to enable to induce triggering or to have a dark count rate that is higher than the dark count rate of the further single-photon avalanche diode.

Abstract: A Hall sensor (HS) comprises at least four sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) for connecting the Hall sensor (HS) in at least two Hall sensing elements (11, 12, . . . , 44) connected together, element terminals (A, B, C, D) of the Hall sensing elements (11, 12, . . . , 44) are connected in between the sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D). Each of the Hall sensing elements (11, 12, . . . , 44) is configured to provide an individual sensor value between two of its element terminals (A, B, C, D). The at least two Hall sensing elements (11, 12, . . . , 44) are distributed basically equally into two halves (B1, B2) and are connected such that a difference value is electrically formed between two of the sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) resulting from the respective individual sensor values.

Abstract: The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).

Abstract: A Hall sensor comprises at least three Hall sensor elements (1, 2, . . . , 94) that respectively comprise at least three element terminals (A, B, C, D, E, F, G, H) and are interconnected in a circuit grid with a structure that is more than one-dimensional, as well as at least three sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) for contacting the Hall sensor. In this case, each sensor terminal (EXT_A, EXT_B, EXT_C, EXT_D) is connected to at least one of the Hall sensor elements (1, 2, . . . , 94) at one of its element terminals (A, B, C, D, E, F, G, H).

Abstract: According to a method for operating a Hall sensor assembly, at least two values (I1, I2) of an input signal (I) of a Hall sensor (11) of the Hall sensor assembly (10) having different magnitudes are set and the associated values (V1, V2) of an output signal (V) of the Hall sensor (11) are determined. Furthermore, a residual offset value (k, VOFF) of the output signal (V) is determined according to the values (V1, V2) of the output signal (V) that were determined at the at least two values (I1, I2) of the input signal (I).

Abstract: The Hall sensor semiconductor component comprises an arrangement of at least two Hall sensors (1, 2) with signal connections (11, 13, 21, 23) and supply connections (12, 14, 22, 24), and a switching network, which varies the positions of the supply connections in successive phases and connects the Hall sensors in series in each phase via the respective signal connections.

Abstract: An isolation area (10) is provided over a drift region (12) with a spacing (d) to a contact area (4) provided for a drain connection (D). The isolation area is used as an implantation mask, in order to produce a dopant profile of the drift region in which the dopant concentration increases toward the drain. The implantation of the dopant can be performed instead before the production of the isolation area, and the later production of the isolation area (10) changes the dopant profile also in a way that the dopant concentration increases toward the drain.

Abstract: A high-voltage NMOS transistor with low threshold voltage. The body doping that defines the channel region is in the form of a deep p-well. An additional shallow p-doping is arranged as a channel stopper on the transistor head. This additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.

Abstract: A Hall sensor (HS) comprises at least four sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) for connecting the Hall sensor (HS) in at least two Hall sensing elements (11, 12, . . . , 44) connected together, element terminals (A, B, C, D) of the Hall sensing elements (11, 12, . . . , 44) are connected in between the sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D). Each of the Hall sensing elements (11, 12, . . . , 44) is configured to provide an individual sensor value between two of its element terminals (A, B, C, D). The at least two Hall sensing elements (11, 12, . . . , 44) are distributed basically equally into two halves (B1, B2) and are connected such that a difference value is electrically formed between two of the sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) resulting from the respective individual sensor values.

Abstract: A Hall sensor comprises at least three Hall sensor elements (1, 2, . . . , 94) that respectively comprise at least three element terminals (A, B, C, D, E, F, G, H) and are interconnected in a circuit grid with a structure that is more than one-dimensional, as well as at least three sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) for contacting the Hall sensor. In this case, each sensor terminal (EXT_A, EXT_B, EXT_C, EXT_D) is connected to at least one of the Hall sensor elements (1, 2, . . . , 94) at one of its element terminals (A, B, C, D, E, F, G, H).