Patents by Inventor Georg SCHINNER

Georg SCHINNER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11495680
    Abstract: Described herein is a power semiconductor device and corresponding method of production. The semiconductor device includes: a power device region formed in a semiconductor substrate and including first trenches and second trenches extending lengthwise in parallel with one another with semiconductor mesas between adjacent ones of the trenches, each first trench including a gate electrode at a first potential and each second trench including a field plate at a second potential; and a current sense region formed in the semiconductor substrate. A subset of the first trenches, a subset of the second trenches and a subset of the semiconductor mesas are common to both the current sense region and the power device region. The second trenches are interrupted along opposite first and second sides of the current sense region such that the field plates are interrupted between the power device region and the current sense region.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 8, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Matteo Dainese, Georg Schinner, Frank Wolter
  • Patent number: 11393736
    Abstract: A method of manufacturing a semiconductor device includes: forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells; forming a first dielectric material over the first and second regions; forming a second dielectric material over the first dielectric material; forming a pn diode in the first dielectric material over the second region; etching first contact grooves into a p-type region of the pn diode, second contact grooves into an n-type region of the pn diode, and third contact grooves into the first region of the semiconductor substrate at the same time using a common contact formation process; and filling the first contact grooves, the second contact grooves and the third contact grooves with an electrically conductive material.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Mark Harrison, Georg Schinner
  • Patent number: 11394378
    Abstract: An integrated circuit comprises a power switch comprising a current path and a current sense node; and a temperature sense circuit internally coupled between the current path and the current sense node.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 19, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Tomas Manuel Reiter, Georg Schinner, Frank Wolter
  • Publication number: 20220165879
    Abstract: Described herein is a power semiconductor device and corresponding method of production. The semiconductor device includes: a power device region formed in a semiconductor substrate and including first trenches and second trenches extending lengthwise in parallel with one another with semiconductor mesas between adjacent ones of the trenches, each first trench including a gate electrode at a first potential and each second trench including a field plate at a second potential; and a current sense region formed in the semiconductor substrate. A subset of the first trenches, a subset of the second trenches and a subset of the semiconductor mesas are common to both the current sense region and the power device region. The second trenches are interrupted along opposite first and second sides of the current sense region such that the field plates are interrupted between the power device region and the current sense region.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: Matteo Dainese, Georg Schinner, Frank Wolter
  • Publication number: 20200006185
    Abstract: A method of manufacturing a semiconductor device includes: forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells; forming a first dielectric material over the first and second regions; forming a second dielectric material over the first dielectric material; forming a pn diode in the first dielectric material over the second region; etching first contact grooves into a p-type region of the pn diode, second contact grooves into an n-type region of the pn diode, and third contact grooves into the first region of the semiconductor substrate at the same time using a common contact formation process; and filling the first contact grooves, the second contact grooves and the third contact grooves with an electrically conductive material.
    Type: Application
    Filed: August 30, 2019
    Publication date: January 2, 2020
    Inventors: Mark Harrison, Georg Schinner
  • Publication number: 20190273488
    Abstract: An integrated circuit comprises a power switch comprising a current path and a current sense node; and a temperature sense circuit internally coupled between the current path and the current sense node.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 5, 2019
    Inventors: Tomas Manuel Reiter, Georg Schinner, Frank Wolter
  • Publication number: 20190172770
    Abstract: A semiconductor device includes a semiconductor substrate having a first region with one or more transistor cells and a second region devoid of transistor cells, a first dielectric material over the first region and the second region of the semiconductor substrate, a second dielectric material over the first dielectric material, a pn diode formed in the first dielectric material over the second region of the semiconductor substrate, a plurality of first contacts extending from above the pn diode and into a p-type region of the pn diode so that the p-type region abuts sidewalls of each first contact, and a plurality of second contacts extending from above the pn diode and into an n-type region of the pn diode so that the n-type region abuts sidewalls of each second contact.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Inventors: Mark Harrison, Georg Schinner
  • Patent number: 10276362
    Abstract: According to various embodiments, a method for processing a semiconductor region, wherein the semiconductor region comprises at least one precipitate, may include: forming a precipitate removal layer over the semiconductor region, wherein the precipitate removal layer may define an absorption temperature at which a chemical solubility of a constituent of the at least one precipitate is greater in the precipitate removal layer than in the semiconductor region; and heating the at least one precipitate above the absorption temperature.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Evelyn Napetschnig, Sandra Wirtitsch, Mario Barusic, Aleksander Hinz, Robert Hartl, Georg Schinner
  • Publication number: 20170316934
    Abstract: According to various embodiments, a method for processing a semiconductor region, wherein the semiconductor region comprises at least one precipitate, may include: forming a precipitate removal layer over the semiconductor region, wherein the precipitate removal layer may define an absorption temperature at which a chemical solubility of a constituent of the at least one precipitate is greater in the precipitate removal layer than in the semiconductor region; and heating the at least one precipitate above the absorption temperature.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: Evelyn NAPETSCHNIG, Sandra WIRTITSCH, Mario BARUSIC, Aleksander HINZ, Robert HARTL, Georg SCHINNER