Abstract: An interface apparatus is provided having a first register device and a second register device, which is connected in parallel with it. The register devices are configured to receive a data word. The interface apparatus includes a synchronization circuit, to which a first and a second clock signal is supplied and which is configured to emit a selection signal, which is derived from the first clock signal, for selection of the first or second register device for storage of a data word. The synchronization circuit is also configured to emit a control signal derived from the selection signal and the second clock signal, at a control output. The control output is coupled to a selection circuit, by means of which the output of one of the two register devices can be connected to the data output of the interface apparatus. Comparison of the selection signal with the second clock signal means that there is no need for an additional registration device.

Abstract: A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance element (22) is formed by one or more varactors whose capacitance can be adjusted by an analogue adjusting voltage (Vtune), while a second capacitance element (23) is formed by an arrangement comprising a plurality of capacitors which can be actuated by a digital bit word VCWD[N:1]. Digital calibration for the VCO (20) is performed by determining whether the present adjusting voltage is within a particular voltage range and, if this is not the case, the digital bit word being incremented or decremented by a bit value.

Abstract: An interface apparatus is provided having a first register device and a second register device, which is connected in parallel with it. The register devices are configured to receive a data word. The interface apparatus includes a synchronization circuit, to which a first and a second clock signal is supplied and which is configured to emit a selection signal, which is derived from the first clock signal, for selection of the first or second register device for storage of a data word. The synchronization circuit is also configured to emit a control signal derived from the selection signal and the second clock signal, at a control output. The control output is coupled to a selection circuit, by means of which the output of one of the two register devices can be connected to the data output of the interface apparatus. Comparison of the selection signal with the second clock signal means that there is no need for an additional registration device.

Abstract: A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance element (22) is formed by one or more varactors whose capacitance can be adjusted by an analogue adjusting voltage (Vtune), while a second capacitance element (23) is formed by an arrangement comprising a plurality of capacitors which can be actuated by a digital bit word VCWD[N:1]. Digital calibration for the VCO (20) is performed by determining whether the present adjusting voltage is within a particular voltage range and, if this is not the case, the digital bit word being incremented or decremented by a bit value.