Patents by Inventor Georg Talut

Georg Talut has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device with superior crack resistivity in the metallization system
    Patent number: 10340229
    Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dirk Breuer, Georg Talut
  • SEMICONDUCTOR DEVICE WITH SUPERIOR CRACK RESISTIVITY IN THE METALLIZATION SYSTEM
    Publication number: 20190109097
    Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.
    Type: Application
    Filed: October 11, 2017
    Publication date: April 11, 2019
    Inventors: Dirk Breuer, Georg Talut
  • Vertical breakdown protection layer
    Patent number: 9362239
    Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Oliver Aubel, Georg Talut, Thomas Werner
  • VERTICAL BREAKDOWN PROTECTION LAYER
    Publication number: 20160111382
    Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 21, 2016
    Inventors: Oliver Aubel, Georg Talut, Thomas Werner