Abstract: An apparatus and a method for the synchronization of an asynchronous signal in synthesis and simulation of a clocked circuit are disclosed, in which a circuit to be simulated and tested is described with a hardware description language and the asynchronous signals present therein are marked. For producing a network list, the hardware description language is processed with a synthesis tool, in which a specific synchronization module is inserted at every marking. For testing the time behavior of the signals in the clocked circuit on the basis of the network list, a simulator implements a logic/timing simulation, in which a test of the time behavior is selectively deactivated for each inserted synchronization module. The unknown statusses that still occur are output via a display.

Abstract: A circuit for spike-free clock switching which offers asynchronous switching between two clock signals of the same frequency and of any desired phase angle, which is purely digital, which can be fully implemented in an integrated module, and which avoids spikes/glitches during switching.

Abstract: A hydraulic control for a dividing machine tool, in particular a shear or cutting press, in which a damping device is provided in order to counteract a sudden downward movement of the working piston upon the cutting through of a workpiece during an operating stroke.