Abstract: A driver circuit (100) is utilized to drive a high current load (116) in an electronic device powered by a battery (118) having a terminal voltage which varies in relation to a level of energy being consumed. The driver circuit (100) includes a differential amplifier (110) which is responsive to a predetermined reference voltage and to the terminal voltage for generating a drive control signal which proportionally reduces a current supplied to the high current load (114) when the terminal voltage is substantially equal to and lower than the predetermined reference voltage. A slope control element (112) is coupled to the differential amplifier (110) to control a rate at which the drive control signal reduces proportionally the current supplied to the high current load (116). A load control element (114), coupled to the differential amplifier (100), provides the supply of current to the high current load (116).

Abstract: In a device having a primary battery 10, a first voltage multiplier 20 is used to power digital electrical circuits 40 from the primary battery, and a second voltage multiplier 100-136 is used to recharge a backup battery 50 from the primary battery. The backup battery is charged to a voltage greater than the voltage generated by the first voltage multiplier. Methods of controlling the second voltage multiplier reduce its interference in measurement of device parameters, and reduce the power consumed from the primary battery.

Abstract: A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.