Abstract: A method for cooling a turbine shroud assembly includes providing a turbine shroud assembly including a shroud segment having a leading edge, a trailing edge and a midsection defined therebetween. A shroud support circumferentially spans and supports the shroud segment. The shroud support includes a forward hanger coupled to the leading edge, a midsection hanger coupled to the midsection and an aft hanger coupled to the trailing edge. An annular shroud ring structure includes a midsection position control ring coupled to the midsection hanger and an aft position control ring coupled to the aft hanger. Cooling air is extracted from a compressor positioned upstream of the turbine shroud assembly.

Abstract: A method is provided for reducing semiconductor memory wordline propagation delays of long wordlines by inserting pipeline registers in the wordlines between groups of memory cells.

Abstract: A frequency synthesis phase-locked loop architecture using a regenerative sampling latch is described. The frequency divider typically employed in the feedback path of a frequency synthesis phase-locked loop is replaced by a regenerative sampling latch with a binary output. The regenerative sampling latch subsamples the frequency synthesizer output to produce a low-frequency aliased signal that can be processed further or directly used to lock the phase-locked loop. This architecture is referred to as an alias-locked loop. The relaxed constraints on the regenerative sampling latch make it possible to create high-speed frequency synthesizer phase-locked loops without the suffering the limitations imposed by traditional dividers connected directly to the oscillator output.

Abstract: A high-density dynamic memory device with compact sense amplifier circuit is described. The memory device achieves high density through the use of a compact sense amplifier circuit that employs a single transistor to sense stored dynamic data. Functionality of the device is enabled by an architecture and method of operation that support a compact sense amplifier circuit. Enabling techniques include sequential sensing of memory columns, a two-pass write operation, a two-step refresh operation, a reference scheme that uses reference data stored in regular memory cells, and the application of digital signal processing to determine sensed data and cancel crosstalk noise.

Abstract: A method for cooling a turbine shroud assembly includes providing a turbine shroud assembly including a shroud segment having a leading edge, a trailing edge and a midsection defined therebetween. A shroud support circumferentially spans and supports the shroud segment. The shroud support includes a forward hanger coupled to the leading edge, a midsection hanger coupled to the midsection and an aft hanger coupled to the trailing edge. An annular shroud ring structure includes a midsection position control ring coupled to the midsection hanger and an aft position control ring coupled to the aft hanger. Cooling air is extracted from a compressor positioned upstream of the turbine shroud assembly.

Abstract: The present invention relates to an ultraviolet light-curable polymer resin-impregnated fibre composite sheet. In some embodiments, the composite sheet comprises polymer resins mixed with glass fibre to form polymer resin-impregnated glass fibre composites. The invention extends to methods of preparing the polymer composite, and to various applications thereof, and also to an apparatus suitable for the manufacture of the polymer composite.

Abstract: A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.

Abstract: The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical. Only one mask set and wafer type is required since a single circuit design is produced for one die in the stack and reused for all the dies with little or no modification. The system scales directly as the level of stacking is increased while incurring no extra design effort, beyond that required for the initial design.

Abstract: A wrapper-strap for a sandwich, wherein the wrapper-strap is made of elongate foldable sheet material. The sheet material is shaped and dimensioned to fit snugly belt-fashion around the sandwich. The wrapper-strap has complementary first and second fastening formations, towards opposed ends thereof. The fastening formations permit the wrapper-strap to be fitted snugly around the sandwich by fastening the two fastening formations together.

Abstract: A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.

Abstract: A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory columns and their associated processing elements are disabled, by setting a bypass circuit within the processing element to be disabled. An address remapping circuit ensures that spare memory columns and associated processing elements replacing the defective memory columns and processing elements can be addressed in a linear column order. The column redundancy architecture is flexible as it permits replacement of arbitrary numbers of series adjacent processing elements as well as non adjacent processing elements with a minimal impact on device performance.

Abstract: The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical. Only one mask set and wafer type is required since a single circuit design is produced for one die in the stack and reused for all the dies with little or no modification. The system scales directly as the level of stacking is increased while incurring no extra design effort, beyond that required for the initial design.

Abstract: A chuck secures a rigid coaxial cable to a reference machine plane. A rotatable pressure die automatically engages and bends the cable relative to both a bend die, which is rotatable about a fixed axis, and a fixed support die. The support die absorbs the brunt of the bend forces created by the pressure die and supports the cable as it is displaced by the machine carriage between bending operations. A cable clamp automatically selectively holds the cable and is lowered out of the way of the chuck to permit bending of the cable close to the chuck. The clamp jaws, pressure die, and chuck are adjustable to preclude damage to the cable.

Abstract: A telephone switching system for telephone trunk and subscriber lines that carry voice and associated supervisory information signals. The voice signals are received through one of a plurality of ports under the control of a port event processor, and are transferred through a switching arrangement under the control of a call processor for transmission through a second port. The supervisory information is received with the associated voice signals, and is sampled and stored in a port data store memory. The call processor can retrieve or modify the supervisory information stored in the port data memory store, and can store control information in the port data store. The port event processor enables the transfer of certain supervisory information from the port data store for transmission with the associated voice signals to the respective port. The port event processor also performs certain operations specified by the commands and supervisory information stored in the port data store memory.

Abstract: A ring trip circuit adapted for use in a community office switching system that includes a call control processor and a port event processor. The call control processor and port event processor interact through a port storage unit that contains information corresponding to each telephone line connected to the switching system. The switching system also includes a ringing generator for transmitting ringing signals onto a telephone line to a called party. Windings for a common bridge relay connect in circuit with each telephone line and diodes shunt the windings so the relay responds only to signals of one polarity. The contacts of the common bridge relay, therefore, reflect the duty cycle of the signal through the common bridge relay and this duty cycle varies when the called party goes off-hook during a ringing burst. The common bridge relay produces a supervisory signal that is sampled and transferred, for each telephone line, to a corresponding port storage area.

Abstract: The present invention provides a method for the prevention of renal papillary necrosis induced by non-steroidal anti-inflammatory compounds (NOSAC) comprising the administration of certain prostaglandins.

Abstract: The diphthalocyanines of certain tri- and tetravalent metals, especially those of the empirical general formulae (PC).sub.2 H.M.sup.III (Ia) or (PC).sub.2. M.sup.IV (Ib) (wherein M.sup.III and M.sup.IV represent respectively the tri- and tetravalent metal, and "PC" represents the phthalocyanine ring system) are well-known for their semiconductor and/or electrochromic properties. They are presently prepared by a process in which an organic derivative of the metal (an acetate, for example) is reacted, at about 300.degree. C. in a sealed tube, with an appropriate phthalonitrile. This process is itself unsatisfactory, and the invention provides a novel preparative process, process technique and application method.