Patents by Inventor George A. Gonzalez

George A. Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for addressing and improving holds in logic networks
    Patent number: 8347250
    Abstract: A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George A. Gonzalez, Pete J. Hannan, William A. McGee, Vasant Palisetti, Ashok Venkatachar
  • METHOD AND APPARATUS FOR ADDRESSING AND IMPROVING HOLDS IN LOGIC NETWORKS
    Publication number: 20120167030
    Abstract: A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: George A. Gonzalez, Pete J. Hannan, William A. McGee, Vasant Palisetti, Ashok Venkatachar