Abstract: A synchronous buck regulator controller is provided. The regulator controller includes switch control circuitry, an unloading event detection circuit, an inductor current detection circuit, and a synchronous switch control logic circuit. In operation, the regulator controller controls a main switch and a synchronous switch to control the buck regulation. The unloading event detection circuit is arranged to detect an unloading event, and to assert an unloading event signal if such an event is detected. The inductor current detection circuit is arranged to assert an inductor current detection signal if the inductor current is close to zero. The synchronous switch control logic circuit is arranged to block the synchronous switch from turning on if the unloading event signal is asserted and the inductor current detection signal is not asserted.

Abstract: A synchronous switching voltage regulator circuit is provided. After the first PWM pulse or at the end of a soft-start, a gradual transition is made from asynchronous rectification to fully synchronous rectification, or vice versa. During the gradual transition, the error voltage is level-shifted down to correct for error caused by reverse current through the body diode of the main switch.

Abstract: A current difference circuit is provided. The currents difference circuit provides an output current that is the difference of two input currents, while employing feedforward to clamp the output current. The current difference circuit brings the lower of the two input currents along with the higher of the two such that the difference between them is always constant if the difference is beyond the clamp range.

Abstract: Method and circuit for automatic correction of emulated inductor current without knowledge of actual inductor current ramp for an emulated current mode (ECM) PWM switching regulator. In an ECM-PWM switching regulator a compensation ramp component is usually added to an up-slope. An excess ramp component may also be added compared to actual inductor current. According to one embodiment of the present invention, an integrating negative feedback circuit is employed to reduce both extra components. According to another embodiment, a single integrating negative feedback loop is added to the ECM-PWM regulator to retain the compensation ramp component while reducing the excess ramp component. According to a further embodiment, excess ramp component is reduced by adding the integrating negative feedback loop at an end stage of the circuit. Finally, the feedback loop with two duplicate track-and-hold circuitry may be added to reduce the excess ramp component, while retaining the compensation component.

Abstract: Method and circuit for automatic correction of emulated inductor current without knowledge of actual inductor current ramp for an emulated current mode (ECM) PWM switching regulator. In an ECM-PWM switching regulator a compensation ramp component is usually added to an up-slope. An excess ramp component may also be added compared to actual inductor current. According to one embodiment of the present invention, an integrating negative feedback circuit is employed to reduce both extra components. According to another embodiment, a single integrating negative feedback loop is added to the ECM-PWM regulator to retain the compensation ramp component while reducing the excess ramp component. According to a further embodiment, excess ramp component is reduced by adding the integrating negative feedback loop at an end stage of the circuit. Finally, the feedback loop with two duplicate track-and-hold circuitry may be added to reduce the excess ramp component, while retaining the compensation component.

Abstract: A method and circuit for synchronizing an input clock signal with a plurality of internal clock signals in a multiple phase Pulse Width Modulation (PWM) switching power supply without using a Phase Locked Loop (PLL). A period of the input clock signal is measured by using a frequency to voltage converter. A reference capacitor charged by a constant current source is arranged to generate a reference voltage with a slope based on the period of the input clock signal. A change in the reference voltage across the reference capacitor is substantially inversely proportional to a frequency of the input clock. By providing the reference voltage to a sample-and-hold circuit and using an output of the sample-and-hold circuit to feed a comparator, synchronization may be accomplished. Each internal clock signal is generated by different reference capacitor and current source circuit.