Patents by Inventor George A. Mann

George A. Mann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6529862
    Abstract: In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: March 4, 2003
    Assignee: Bull HN Information Systems Inc.
    Inventors: George A. Mann, Bruce A. Noyes, Rene-Joseph Chevance
  • Patent number: 6516295
    Abstract: In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: February 4, 2003
    Assignee: Bull HN Information Systems Inc.
    Inventors: George A. Mann, Bruce A. Noyes, Rene-Joseph Chevance
  • Patent number: 6457171
    Abstract: In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: September 24, 2002
    Assignee: Bull HN Information Systems Inc.
    Inventors: George A. Mann, Bruce A. Noyes, Rene-Joseph Chevance
  • Patent number: 6339752
    Abstract: When emulating a Target architecture on a Host system having a different architecture, virtual-to-real address translation is typically expensive in terms of computer cycles. The cost for translating addresses for instruction fetches can be significantly reduced by maintaining both a virtual and a real memory address instruction counter. Both are incremented on each instruction fetch. Virtual to real address translation is eliminated as long as execution continues on the same real memory page of instructions. Alternatively, only a real memory address instruction counter is incremented, while maintaining a delta instruction counter value to efficiently translate back and forth to and from the corresponding virtual memory address.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: January 15, 2002
    Assignee: Bull HN Information Systems Inc.
    Inventors: George A. Mann, Bruce E. Hayden