Patents by Inventor George A. Pearce
George A. Pearce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7700977Abstract: An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.Type: GrantFiled: February 26, 2008Date of Patent: April 20, 2010Assignee: Intersil Americas Inc.Inventors: Michael David Church, Alexander Kalnitsky, Lawrence George Pearce, Michael Ray Jayne, Thomas Andrew Jochum
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Publication number: 20080315329Abstract: An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.Type: ApplicationFiled: February 26, 2008Publication date: December 25, 2008Applicant: Intersil Americas Inc.Inventors: MICHAEL DAVID CHURCH, Alexander Kalnitsky, Lawrence George Pearce, Michael Ray Jayne, Thomas Andrew Jochum
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Publication number: 20080150358Abstract: A apparatus and method of operating a power converter circuit is provided. The method selectively couples control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of the plurality of output ports. Wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals.Type: ApplicationFiled: March 3, 2008Publication date: June 26, 2008Applicant: INTERSIL AMERICAS INC.Inventor: Lawrence George Pearce
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Patent number: 7345378Abstract: A power supply circuit contains a plurality of DC-DC converter control loops that provide respectively different control signals. A plurality of output driver stages of given current drive capabilities have their inputs programmably connectable via a set of switches to control signals that may be generated by any of the converter control loops. The output of each output driver stage is externally selectively connectable to any of plural output voltage ports, so that each output voltage port is capable of supplying any of the respectively different output voltages associated with the voltage control signals generated by the DC-DC converter control loops, and has an output current capability that depends upon which output driver stages are coupled to it.Type: GrantFiled: December 7, 2004Date of Patent: March 18, 2008Assignee: Intersil Americas Inc.Inventor: Lawrence George Pearce
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Patent number: 7141941Abstract: In order to minimize switching-induced electromagnetic interference in a power supply switching circuit of the type used to control the AC power for multiple high voltage devices, such as cold cathode fluorescent lamps employed for backlighting a large scale liquid crystal display, the gating signals that are used to switch lamp-driving inverter circuits ON and OFF are staggered, or slightly offset in time, so that no two switching devices will be switched at the same time. By slightly offset in time is meant that the time differential between any pair of switching signals is relatively small compared to the period of the switching signal frequency. This has the effect of spreading out and thereby diminishing the magnitude of the spectral content of both capacitively and inductively coupled transients that are produced at switching times of the inverter circuits.Type: GrantFiled: October 19, 2004Date of Patent: November 28, 2006Assignee: Intersil Americas Inc.Inventors: Robert L. Lyle, Jr., Lawrence George Pearce
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Patent number: 6906536Abstract: An arrangement for measuring current through a phase section of a buck mode DC-DC converter includes an auxiliary integrated circuit containing an auxiliary power MOSFET and a pilot MOSFET coupled in parallel with a current path through a high side MOSFET of a half-bridge of the converter. The pilot MOSFET has a current path coupled to a current measurement terminal. The MOSFETs of the auxiliary circuit are time division multiplexed with the high side MOSFET, whereby a determination of current through the auxiliary high side MOSFET is based upon current through the pilot device and the geometric ratio of the size of the pilot device to that of the high side auxiliary MOSFET. The high side MOSFET is activated for a large number of switching cycles relative to the pilot circuitry, but the pilot circuitry is activated sufficiently often to derive a relatively accurate measure of current flow.Type: GrantFiled: November 24, 2003Date of Patent: June 14, 2005Assignee: Intersil Americans Inc.Inventors: Lawrence George Pearce, William David Bartlett
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Publication number: 20040196055Abstract: An arrangement for measuring current through a phase section of a buck mode DC-DC converter includes an auxiliary integrated circuit containing an auxiliary power MOSFET and a pilot MOSFET coupled in parallel with a current path through a high side MOSFET of a half-bridge of the converter. The pilot MOSFET has a current path coupled to a current measurement terminal. The MOSFETs of the auxiliary circuit are time division multiplexed with the high side MOSFET, whereby a determination of current through the auxiliary high side MOSFET is based upon current through the pilot device and the geometric ratio of the size of the pilot device to that of the high side auxiliary MOSFET. The high side MOSFET is activated for a large number of switching cycles relative to the pilot circuitry, but the pilot circuitry is activated sufficiently often to derive a relatively accurate measure of current flow.Type: ApplicationFiled: November 24, 2003Publication date: October 7, 2004Applicants: Intersil Americas Inc., State of Incorporation: DelawareInventors: Lawrence George Pearce, William David Bartlett
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Patent number: 6012828Abstract: A device (10) for attaching a light to a trailer hitch frame (172). The device (10) is comprised of a lamp assembly (12) that attaches to an adjustable lamp attachment assembly (40) which allows the lamp assembly (12) to be adjusted radially and in elevation. The lamp assembly (12) is attached to a trailer hitch frame attachment bracket (64) that is dimensioned to fit over a trailer hitch frame (172) that can range in size from 1.25 square inches to 4.0 square inches (3.2 to 10.2 cm). The frame attachment bracket (64) is attached to the trailer hitch frame (172) by means of two nylon tie wraps (136,144). The tie wraps, which are secured to the bracket (64), are wrapped around the trailer hitch frame (172) and are locked in place. After the bracket (64) is secured to the trailer hitch frame (172), the device (10) is connected to the vehicle electrical circuit that controls the vehicle rear lights.Type: GrantFiled: December 8, 1997Date of Patent: January 11, 2000Inventors: George A. Pearce, Sam Fu, Calvin S. Wang
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Patent number: 5920108Abstract: Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.Type: GrantFiled: November 7, 1996Date of Patent: July 6, 1999Assignee: Harris CorporationInventors: Donald Frank Hemmenway, Lawrence George Pearce
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Patent number: 5872044Abstract: Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.Type: GrantFiled: October 17, 1996Date of Patent: February 16, 1999Assignee: Harris CorporationInventors: Donald Frank Hemmenway, Lawrence George Pearce
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Patent number: 5777362Abstract: A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices.Type: GrantFiled: June 7, 1995Date of Patent: July 7, 1998Assignee: Harris CorporationInventor: Lawrence George Pearce
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Patent number: 5689129Abstract: A power MOS switch (40) is an array of MOS devices that includes alternating drain columns and source columns. Each drain column includes a plurality of separate drain regions (300) that are closely spaced one from another, and each source column includes a continuous narrow elongated source distribution region (302) that extends the length of the column. A plurality of narrow source distribution branch regions (302) are connected to the elongated region and extend transversely from the elongated region at least partially between each separate drain region in each drain column adjacent to the source column. A gate region (303) separates the drain regions in each column from the adjacent source distribution regions.Type: GrantFiled: June 7, 1995Date of Patent: November 18, 1997Assignee: Harris CorporationInventor: Lawrence George Pearce
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Patent number: 5684305Abstract: An isolated pilot transistor 100 for a QVDMOS device 10 has a gate and drain region in symmetry with the sources 20 of device 10 and an additional resistance 116 in the drain 118 to compensate for current spreading between the source 120 and the buried layer resistor 132.Type: GrantFiled: June 7, 1995Date of Patent: November 4, 1997Assignee: Harris CorporationInventor: Lawrence George Pearce