Patents by Inventor George A. Spix
George A. Spix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6195676Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.Type: GrantFiled: January 11, 1993Date of Patent: February 27, 2001Assignee: Silicon Graphics, Inc.Inventors: George A. Spix, Diane M. Wengelski, Stuart W. Hawkinson, Mark D. Johnson, Jeremiah D. Burke, Keith J. Thompson, Gregory G. Gaertner, Giacomo G. Brussino, Richard E. Hessel, David M. Barkai, Steve S. Chen, Steven G. Oslon, Robert E. Strout, II, Jon A. Masamitsu, David M. Cox, Linda J. O'Gara, Kelly T. O'Hair, David A. Seberger, James C. Rasbold, Timothy J. Cramer, Don A. Van Dyke, Ashok Chandramouli
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Patent number: 5745721Abstract: A scalar/vector processor capable of concurrent scaler and vector operations includes scalar resources to process scalar instructions, and vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions. The scalar resources include scalar registers, and the vector resources include vector registers. Decoding means decodes each of a number of address fields. Each field represents a register address to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below a selected moveable address value within a range of addresses encompassed by the address field.Type: GrantFiled: June 7, 1995Date of Patent: April 28, 1998Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5717881Abstract: An improved high performance hardwired supercomputer data processing apparatus includes instruction means adpated to issue one and two parcel instructions. Instruction fetch means provides an instruction stream of two parcel items in sequence. Instruction decode means is responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction or two one parcel instructions, for issuing each two parcel instruction for execution during the one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during the one clock cycle and the next succeeding clock cycle.Type: GrantFiled: June 7, 1995Date of Patent: February 10, 1998Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5706490Abstract: A delayed branch mechanism maintains the flow of an instruction pipeline in a scalar/vector processor having an instruction cache and including instruction fetch means, a program counter, and instruction decode/issue means coupled to the instruction cache by means of the instruction pipeline. Conditional branch instructions are rated as likely conditional branch instructions or unlikely conditional branch instructions based on a probability that their branch conditions will be met. A number of pipeline clock periods required for testing the branch conditions are determined. The likely conditional branch instructions are issued and executed including transferring a branch-to-address to the program counter during the number of pipeline clock periods irrespective of a successful meeting of the branch conditions. A number of useful instructions sufficient to issue within the number of pipeline clock periods are placed into the instruction stream following the likely conditional branch instructions.Type: GrantFiled: June 7, 1995Date of Patent: January 6, 1998Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5659706Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.Type: GrantFiled: June 7, 1995Date of Patent: August 19, 1997Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5640524Abstract: A vector processing system includes a main memory, vector registers, vector resources for accessing memory to transfer vector data between main memory and the vector registers and to perform operations on the vector data. Data words stored in non-consecutive address locations of a segment of main memory are accessed for processing. Offset address values of a number of the data words are stored in consecutive elements of a first vector register. A vector gather instruction is executed which adds each offset address value to a base address value to calculate main memory addresses representing main memory storage locations of the data words, retrieves the data words from the main memory, and stores the data words in consecutive elements of a second vector register in an order corresponding to that in which the offset address values are stored in the first vector register.Type: GrantFiled: February 28, 1995Date of Patent: June 17, 1997Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5623650Abstract: A sequence of conditional vector IF statements is processed by employing a mask register and a condition register. Each conditional vector IF statement is typically performed on two vector registers, each having vector elements. A first conditional vector IF statement in the sequence is processed for those vector elements corresponding to set bits in the mask register. Bits are set in the condition register to reflect those vector elements which correspond to the set bits in the mask register for which the conditional vector IF statement is satisfied. The contents of the condition register are then moved into the mask register. A next conditional vector IF statement in the sequence is then processed for those vector elements corresponding to the new set bits in the mask register. Bits are then set in the condition register to reflect those vector elements which correspond to the new set bits in the mask register for which the conditional vector IF statement is satisfied.Type: GrantFiled: June 7, 1995Date of Patent: April 22, 1997Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5598547Abstract: A vector processor includes functional unit paths, each having an input and an output, and with at least one functional unit path including a plurality of pipelined functional elements coupled to the respective path input and output in parallel. The functional elements have different pipeline lengths to complete processing of operands applied to the path input. Program instruction initiation means responds to a first instruction to initiate processing of first operand data in a first of the functional elements, and responds to a second instruction to initiate the processing of second operand data in a second of the functional elements dependent upon completion of the first instruction but only if the second functional element has a pipeline length equal to or greater than the pipeline length of the first functional element.Type: GrantFiled: June 7, 1995Date of Patent: January 28, 1997Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5561784Abstract: A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.Type: GrantFiled: June 29, 1994Date of Patent: October 1, 1996Assignee: Cray Research, Inc.Inventors: Steve S. Chen, Frederick J. Simmons, George A. Spix, Jimmie R. Wilson, Edward C. Miller, Roger E. Eckert, Douglas R. Beard
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Patent number: 5544337Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.Type: GrantFiled: June 7, 1995Date of Patent: August 6, 1996Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5524255Abstract: A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.Type: GrantFiled: January 27, 1995Date of Patent: June 4, 1996Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, George A. Spix, Edward C. Miller, Robert E. Strout, II, Anthony R. Schooler, Alexander A. Silbey, Brian D. Vanderwarn, Jimmie R. Wilson, Richard E. Hessel, Andrew E. Phelps
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Patent number: 5499356Abstract: A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.Type: GrantFiled: December 28, 1993Date of Patent: March 12, 1996Assignee: Cray Research, Inc.Inventors: Roger E. Eckert, Richard E. Hessel, Andrew E. Phelps, George A. Spix, Jimmie R. Wilson
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Patent number: 5452452Abstract: Method for enabling each of several processors in a multi-processing operating system to schedule processes it will execute without a supervisory scheduler. The processes are executed on the basis of priorities assigned to the processes. More than one processor can schedule processes simultaneously so long as each processor schedules processes having different priority levels from those being processed by another processor.Type: GrantFiled: June 4, 1993Date of Patent: September 19, 1995Assignee: Cray Research, Inc.Inventors: Gregory G. Gaetner, George A. Spix, Diane M. Wengelski, Keith J. Thompson
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Patent number: 5430884Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.Type: GrantFiled: June 11, 1990Date of Patent: July 4, 1995Assignee: Cray Research, Inc.Inventors: Douglas R. Beard, Andrew E. Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey, George A. Spix, Frederick J. Simmons, Don A. Van Dyke
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Patent number: 5428803Abstract: A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters.Type: GrantFiled: July 10, 1992Date of Patent: June 27, 1995Assignee: Cray Research, Inc.Inventors: Steve S. Chen, Douglas R. Beard, George A. Spix, Edward C. Priest, John M. Wastlick, James M. VanDyke
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Patent number: 5388217Abstract: Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory.Type: GrantFiled: December 13, 1991Date of Patent: February 7, 1995Assignee: Cray Research, Inc.Inventors: Gary E. Benzschawel, Lonnie R. Heidtke, Steven S. Chen, Fredrich J. Simmons, George A. Spix
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Patent number: 5339415Abstract: On a tightly coupled multiprocessor computer system, the multiple parallel regions of a multithreaded applications program can execute simultaneously as multiple threads on a plurality of processors. Furthermore, a plurality of multithreaded programs may run simultaneously. The current invention uses an efficient system to schedule and reschedule processors to run these multiple threads. Scheduling is integrated at two levels: at the first level, processors are assigned processes. At the next level, processes are assigned threads. Increased efficiency is achieved by this integration and also by the formation of processes with destructible context. It makes use of shared storage to indicate the process request level and the control state for each parallel region.Type: GrantFiled: November 9, 1992Date of Patent: August 16, 1994Assignee: Cray Research, Inc.Inventors: Robert E. Strout, II, George A. Spix, Jon A. Masamitsu, David M. Cox, Gregory G. Gaertner, Diane M. Wengelski, Keith J. Thompson
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Patent number: 5253359Abstract: Methods and apparatus for a maintenance and control system for sensing and controlling the numerous sections of a highly parallel multiprocessor system. The control and maintenance system communicates with all processors, all peripheral systems, all user interfaces to the multiprocessor system, a system console, and the power and environmental control subsystems.Type: GrantFiled: June 11, 1990Date of Patent: October 12, 1993Assignee: Supercomputer Systems Limited PartnershipInventors: George A. Spix, Glen L. Collier, G. Joseph Throop, David L. Clounch, Cris J. Rhea, Douglas R. Beard
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Patent number: 5239629Abstract: A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routing a signal command generated by the device to a signal dispatch logic and a second switch for receiving signals generated by the signal dispatch logic and routing the signals to the selected device. The signal dispatch logic receiving the signal command, decodes the destination select value and generates a signal to be sent to the selected device. The signal command includes a destination select value representing a device selectably determined by the device. The signaling mechanism also includes an arbitration mechanism connected to the signal dispatch logic and the first switch for resolving simultaneous conflicting signal commands issued by two or more devices.Type: GrantFiled: June 11, 1990Date of Patent: August 24, 1993Assignee: Supercomputer Systems Limited PartnershipInventors: Edward C. Miller, George A. Spix, Anthony R. Schooler, Douglas R. Beard, Alexander A. Silbey, Andrew E. Phelps
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Patent number: 5202988Abstract: Communication among processors having differing operating speeds by providing wake queues in which slower processors can queue entries, access to which by multiple concurrent producers and multiple concurrent consumers is synchronized or controlled using global registers. When a faster processor executes a kernel process for handling a wake queue, an entry is fetched from the wake queue and information stored in the entry is used to process the entry.Type: GrantFiled: August 23, 1990Date of Patent: April 13, 1993Assignee: Supercomputer Systems Limited PartnershipInventors: George A. Spix, Gregory G. Gaertner, Diane M. Wengelski, Keith J. Thompson