Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Abstract: A device may generate a clock signal using spread-spectrum clocking. The spread-spectrum clocking may modulate a frequency of the clock signal to produce a plurality of frequencies for the clock signal during a modulation cycle. The device may receive an instruction to disable the spread-spectrum clocking, and may disable the spread spectrum clocking at the end of the modulation cycle.

Abstract: A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.

Abstract: A device may generate a clock signal using spread-spectrum clocking. The spread-spectrum clocking may modulate a frequency of the clock signal to produce a plurality of frequencies for the clock signal during a modulation cycle. The device may receive an instruction to disable the spread-spectrum clocking, and may disable the spread spectrum clocking at the end of the modulation cycle.

Abstract: A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.

Abstract: A storage and dispensing system including a cabinet having a frame with a plurality of separators, each separator including an opening formed therethrough. The system further includes a plurality of drawers, each drawer having a plurality of compartments configured to store an item therein. Each drawer is positioned adjacent to at least one of the separators and is movable relative to the adjacent separator such that each compartment of each drawer is positionable adjacent to the opening of the associated separator.

Abstract: A memory interface circuit includes a plurality of data bus drivers and logic adapted to be operatively responsive to write driver mask information. If desired, the plurality of bus drivers and the logic may be implemented in separate integrated circuits. The plurality of bus drivers are adapted to be responsive to a write operation. The logic is also adapted to disable any one of the plurality of data bus drivers based on the write driver mask information during the write operation.