Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.

Abstract: Exemplary embodiments are directed to a coexistence of NFC and wireless power functionalities. A device may include an antenna configured to receive a signal. The device may further include a communication circuit configured to selectively couple to the antenna in a default mode of operation. The device may further include a wireless power circuit configured to selectively couple to the antenna in response to detecting that the signal is provided to power or charge a load.

Abstract: The present invention is directed a digital data interface device for transferring digital presentation data at a high rate over a communication link. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. In one example, a cellular telephone having a camera with an MDDI link and a digital data device interface is provided.

Abstract: A method, apparatus, and computer program product embodied on a hardware computer readable storage medium for compensating mismatched delays in at least two signals of a mobile display digital interface (MDDI) system. The method, apparatus, and computer program product embodied on a hardware computer readable storage medium sends a skew calibration packet from a host to a client. The host begins a calibration pattern; then toggling a data signal and a strobe signal at a substantially similar time which strobe signal is used by the client as a clock source. The method, apparatus, and computer program product embodied on a hardware computer readable storage medium also aligns a timing of the strobe signal and the data signal by providing varying delays and resetting the client to an original clock source before a next packet reception.

Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator, a CRC corrupter, an error detector and an error value generator. In one example, the digital transmission link is an MDDI link.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract: The present invention provides a digital data interface device message format that describes command and response messages to be exchanged between a digital device having a system controller and a digital data interface device. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used by a cellular telephone to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. The digital data interface device message format includes a transaction identification field, a count field, a command identification field and a status field. Optionally, the message format can include a data field. When an MDDI link is used, a digital data interface device message can be included in an MDDI register access packet.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: Exemplary embodiments are directed to communication with a wireless power transmitter. A device may include an antenna for wirelessly transmitting a power carrier. The device may further include transmit circuitry coupled to the antenna and configured to transmit a data carrier at a frequency corresponding to at least one harmonic of the power carrier.

Abstract: Exemplary embodiments are directed to a coexistence of NFC and wireless power functionalities. A device may include an antenna configured to receive a signal. The device may further include a communication circuit configured to selectively couple to the antenna in a default mode of operation. The device may further include a wireless power circuit configured to selectively couple to the antenna in response to detecting that the signal is provided to power or charge a load.

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Abstract: Methods and apparatus for providing power efficient time management for mobile media. In an aspect, a method is provided that operates to provide time management for mobile media that is distributed over a network. The method includes receiving the mobile media comprising source video frames that are associated with a source time reference, and capturing a portion of the source video frames. The method also includes re-labeling the portion of the source video frames based on a system time reference to produce synchronized video frames, wherein the network provides communications based on the system time reference, and assembling a transmission frame that comprises the synchronized video frames.

Abstract: A system for noise canceling using a single return conductor. The system employs a first unit, a full duplex communications path coupled to the first unit, and a second unit coupled to the first unit via the full duplex communications path. The full duplex communications path employs at least three conductors: a forward signal carrying conductor; a reverse signal carrying conductor; and a single return conductor. In order to perform noise canceling, the first unit may employ, for example, a first adder coupled to the reverse signal carrying conductor, and a first canceling impedance coupled between the single return conductor and a first unit ground. Similarly, the second unit 12 may employ a second adder coupled to the forward signal carrying conductor, and a second canceling impedance coupled between the single return conductor and a second unit ground.

Abstract: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.