Abstract: A four stage pipelined processor (40) provides efficient processing of the most common operation performed in simulating neuron networks. A first stage of the processor includes a program memory (42) and a program address generator (41). A second stage comprises first and second data memories (44, 46) and respective address generators (60, 66) coupled thereto. A third stage comprises the input (X, Y) of a function unit (82), and a fourth stage comprises the output (Z) of the function unit (82). A unique bus architecture allows the various stages to simultaneously communicate with each other through the use of independent buses, and further provides for the quick simultaneous transfer of data from both the first and second data memories to the function unit. When not needed for performing in the pipelined mode, the various buses may be coupled together and to an I/O interface (52) by means of bus coupling means (e.g., 47).

Abstract: A distributive beam steering computer network for a radar phased array antenna is disclosed which provides direct drive for individual antenna phase shifter elements using a plurality of microcomputers co-located with each phase shifter. The microcomputers calculate the phase shift based on constants stored in a ROM which is located in each microcomputer and phase shift data comprising sin .alpha., sin .beta., and 1/.lambda. signals are distributed to all microcomputers over a single serial data line. The constants required for each shifter are different, and therefore, the ROM in each microcomputer is programmed for a specific location in an array antenna. A phase shift steering command for each element of the phased array antenna is calculated using a shift-and-add multiplication algorithm which is hard-wired into each microcomputer.

Abstract: A distributed, fault-tolerant, self-repairable, reconfigurable signal processing system with redundant elements comprising signal processors, mass memories and input-output controllers interconnected by redundant busses forming a high reliability system. The input-output controller element has redundant busses for interconnecting multiple fault-tolerant distributed signal processing systems into a network configuration. One signal processor element in a system is initially designated as the executive and assigns processing tasks from a mass memory to the other elements or other systems. When a failure is detected, the executive verifies the failure, isolates the faulty element and reassigns the task to another spare element. If another element is not available, the executive reconfigures the system to permit degraded operation using the available elements. The executive element, itself, is fault monitored by one of the other elements which is capable of assuming the role of executive as required.

Abstract: A web tension control comprising a shaped frictional drag means in frictional contact with the edges of at least one side of the web material situated on a supply spool to maintain substantially uniform tension in the web material during its transfer from the supply spool to a take-up spool.