Abstract: A method for insuring that the sidewall of a P+ PN+ layered junction mesa semiconductor structure is tapered smoothly from the P layer to the N+ layer of the structure upon formation thereof by immersion of a wafer comprised of the structure in an etchant of 3% HF and 97% HNO.sub.3, comprising the steps of placing an etch mask dot having a diameter slightly less than the greatest diameter required for the N+ layer above the P+ layer at a preselected site on the wafer, preselecting a specific ratio of etchant quantity to P silicon quantity, immersing the wafer in the preselected quantity of the etchant, and withdrawing the wafer from the etchant at the instant at which the silicon is removed from around the dot.

Abstract: An improved method of manufacturing a semi-conductor device having a lead bonded to a surface thereof, wherein the device is fabricated by removing a section of a substrate which surrounds a surface portion of the substrate comprising the surface to which the lead is bonded, includes bonding the lead to the surface portion of the substrate prior to removing the section.