Patents by Inventor George Apostol, Jr.
George Apostol, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947472Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.Type: GrantFiled: June 28, 2022Date of Patent: April 2, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventors: Shreyas Shah, George Apostol, Jr., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
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Publication number: 20230393997Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Applicant: Elastics.cloud, Inc.Inventors: Shreyas Shah, George Apostol, JR., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
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Publication number: 20230027178Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.Type: ApplicationFiled: June 28, 2022Publication date: January 26, 2023Applicant: Elastics.cloud, Inc.Inventors: Shreyas Shah, George Apostol, Jr., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
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Publication number: 20230017643Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.Type: ApplicationFiled: June 28, 2022Publication date: January 19, 2023Applicant: Elastics.cloud, Inc.Inventors: Shreyas Shah, George Apostol, Jr., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
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Publication number: 20230017583Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.Type: ApplicationFiled: June 28, 2022Publication date: January 19, 2023Applicant: Elastics.cloud, Inc.Inventors: Shreyas Shah, George Apostol, JR., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
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Publication number: 20230012822Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.Type: ApplicationFiled: June 28, 2022Publication date: January 19, 2023Applicant: Elastics.cloud, Inc.Inventors: Shreyas Shah, George Apostol, JR., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
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Patent number: 7653763Abstract: A subsystem (200) is provided at least Direct Memory Access (DMA) device (220) utilized to provide instructions to facilitate the operation of a subsystem processor (210). In one embodiment, a system level processor (102) initiates the provision of instructions for a subsystem (210). The DMA device may be additionally or alternatively utilized to provide data transfer capabilities to a plurality of data channels in a subsystem (200). The DMA device processes channels in a time limited manner to ensure that data is processed in a manner appropriate for time critical data.Type: GrantFiled: February 28, 2002Date of Patent: January 26, 2010Assignee: Cavium Networks, Inc.Inventors: Mileend Gadkari, Harsimran S. Grewal, George Apostol, Jr.
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Patent number: 7436954Abstract: A security subsystem is provided with at least a first security engine, a first set of registers and a control portion to perform a first security operation for each of a first number of data blocks of each of a first number of data segments of a first data object. In one embodiment, the security subsystem is provided with two security engines and two sets of registers to respectively perform the first security operation and a second security operation for the first data object and a similarly constituted second data object. In one embodiment, the first and second security operations are DES and hashing operations. In one embodiment, the multi-method security subsystem is embodied in a multi-service system-on-chip.Type: GrantFiled: February 28, 2002Date of Patent: October 14, 2008Assignee: Cavium Networks, Inc.Inventors: George Apostol, Jr., Peter N. Dinh
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Patent number: 7349424Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively provides paths for the outputs to reach their destinations, to facilitate concurrent communications between at least two selected combinations of the subsystems.Type: GrantFiled: June 16, 2006Date of Patent: March 25, 2008Assignee: PMC-Sierra, Inc.Inventors: George Apostol, Jr., Mahadev S. Kolluru, Tom Vu
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Patent number: 7243179Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.Type: GrantFiled: June 6, 2006Date of Patent: July 10, 2007Assignee: Cavium Networks, Inc.Inventors: George Apostol, Jr., Mahadev S. Kolluru
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Patent number: 7107381Abstract: In a bus interface unit, a first communications interface is provided for the coupling of a first plurality of peripheral devices of different device types to facilitate communication with a selected one of the first plurality of peripheral devices of different device types. In addition, a second communications interface is provided for coupling to a first bus of an integrated circuit (IC) to facilitate communication with a selected one of a second plurality of devices of the IC, via the first bus. A controller is provided for the coupling of the first and second communications interfaces to facilitate communications between selected ones of the first and second plurality of devices, dynamically selecting and employing a communication protocol consistent with the device type of the selected one of the first plurality of peripheral devices. The bus interface unit has particular application to interfacing external devices with the core of an SOC.Type: GrantFiled: November 20, 2002Date of Patent: September 12, 2006Assignee: PMC-Sierra, Inc.Inventors: Jeffrey S. Earl, George Apostol, Jr., Douglas A. Cross
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Patent number: 7095752Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors and a controller, coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively configures itself to provide paths for the outputs to reach their destinations, to facilitate concurrent communications between selected combinations of the subsystems.Type: GrantFiled: February 28, 2002Date of Patent: August 22, 2006Assignee: PMC-Sierra, Inc.Inventors: George Apostol, Jr., Mahadev S. Kolluru, Tom Vu
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Patent number: 7096292Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.Type: GrantFiled: February 28, 2002Date of Patent: August 22, 2006Assignee: Cavium Acquisition Corp.Inventors: George Apostol, Jr., Mahadev S. Kolluru
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Publication number: 20050259823Abstract: A security subsystem is provided with at least a first security engine, a first set of registers and a control portion to perform a first security operation for each of a first number of data blocks of each of a first number of data segments of a first data object. In one embodiment, the security subsystem is provided with two security engines and two sets of registers to respectively perform the first security operation and a second security operation for the first data object and a similarly constituted second data object. In one embodiment, the first and second security operations are DES and hashing operations. In one embodiment, the multi-method security subsystem is embodied in a multi-service system-on-chip.Type: ApplicationFiled: February 28, 2002Publication date: November 24, 2005Inventors: George Apostol Jr, Peter Dinh
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Patent number: 6677786Abstract: A frequency rate multiplier to produce an output with an output frequency as a ratio of an input frequency is described. In one embodiment, the frequency rate multiplier includes an accumulator register to store, based upon a first clock signal having the input frequency, a binary representation of the ratio having a first most significant bit and a second most significant bit, a first adder coupled to the accumulator register in a feedback arrangement to receive the binary representation stored in the accumulator register and, based upon the first clock signal, to repeatedly add the accumulator value to a programmable parameter value representing a component of the output frequency to obtain a first result, a secondary adder coupled between the first adder and the accumulator register to receive the first result and, based upon the second most significant bit, to add a constant value to the first result forming a second result to be stored into the accumulator register.Type: GrantFiled: February 28, 2002Date of Patent: January 13, 2004Assignee: Brecis Communications CorporationInventors: Tore L. Kellgren, George Apostol, Jr., Harsimran S. Grewal
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Patent number: 6247084Abstract: A unified memory system includes a processor, a memory controller, a plurality of bus transactor circuits and a shared memory port. A processor bus is coupled between the processor and the memory controller. A first multiple-bit, bidirectional system bus is coupled between the shared memory port, the memory controller and the plurality of bus transactor circuits. A second multiple-bit, bidirectional system bus is coupled between the memory controller and the plurality of bus transactor circuits.Type: GrantFiled: October 5, 1998Date of Patent: June 12, 2001Assignee: LSI Logic CorporationInventors: George Apostol, Jr., Peter R. Baran, Roderick J. McInnis