Patents by Inventor George Archambault

George Archambault has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080301656
    Abstract: A computer implemented method, apparatus, and computer program product for compiling source code. The source code is scanned to identify a candidate region. A procedure control descriptor is corresponding to the candidate region is generated. The procedure control descriptor identifies, for the candidate region, a condition which, if true at runtime means that the candidate region can be specialized. Responsive to a determination during compile time that satisfaction of at least one condition will be known only at runtime, the procedure control descriptor is used to specialize the candidate region at compile time to create a first version of the candidate region for execution in a case where the condition is true and a second version of the candidate region for execution in a case where the condition is false. Also responsive to the determination, code is further generated to correctly select one of the first region and the second region at runtime.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 4, 2008
    Inventors: Roch Georges Archambault, Shimin Cui, Yaoqing Gao, Raul Esteban Silvera, Peng Zhao
  • Publication number: 20080229297
    Abstract: A computer implemented method, system and computer program product for accessing threadprivate memory for threadprivate variables in a parallel program during program compilation. A computer implemented method for accessing threadprivate variables in a parallel program during program compilation includes aggregating threadprivate variables in the program, replacing references of the threadprivate variables by indirect references, moving address load operations of the threadprivate variables, and replacing the address load operations of the threadprivate variables by calls to runtime routines to access the threadprivate memory. The invention enables a compiler to minimize the runtime routines call times to access the threadprivate variables, thus improving program performance.
    Type: Application
    Filed: May 29, 2008
    Publication date: September 18, 2008
    Applicant: International Business Machines Corporation
    Inventors: ROCH GEORGES ARCHAMBAULT, Shimin Cui
  • Publication number: 20080092125
    Abstract: A target operation in a normalized target loop, susceptible of vectorization and which may, after compilation into a vectorized form, seek to operate on data in nonconsecutive physical memory, is identified in source code. Hardware instructions are inserted into executable code generated from the source code, directing a system that will run the executable code to create a representation of the data in consecutive physical memory. A vector loop containing the target operation is replaced, in the executable code, with a function call to a vector library to call a vector function that will operate on the representation to generate a result identical to output expected from executing the vector loop containing the target operation. On execution, a representation of data residing in nonconsecutive physical memory is created in consecutive physical memory, and the vectorized target operation is applied to the representation to process the data.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 17, 2008
    Inventors: Roch Georges Archambault, George Chochia, Peng Zhao
  • Publication number: 20080092124
    Abstract: A computer implemented method, apparatus, and computer usable program code for compiling source code for performing a complex operation followed by a complex reduction operation. A method is determined for generating executable code for performing the complex operation and the complex reduction operation. Executable code is generated for computing sub-products, reducing the sub-products to intermediate results, and summing the intermediate results to generate a final result in response to a determination that a reduced single instruction multiple data method is appropriate.
    Type: Application
    Filed: October 12, 2006
    Publication date: April 17, 2008
    Inventors: Roch Georges Archambault, Alexandre E. Eichenberger, Amy Kai-Ting Wang, Peng Wu, Peng Zhao
  • Patent number: 7340733
    Abstract: An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operatively coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to store a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Roch Georges Archambault, Robert James Blainey, Charles Brian Hall, Yingwei Zhang
  • Patent number: 7168070
    Abstract: A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: January 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: Roch Georges Archambault, Robert James Blainey, Yaoging Gao, Randall Ray Heisch, Steven Wayne White
  • Patent number: 7100156
    Abstract: A system for optimizing computer code generation by carrying out interprocedural dead store elimination. The system carries out a top down traversal of a call graph in an intermediate representation of the code being compiled. Live on exit (LOE) sets are defined for variables at call points for functions in the code being compiled. Bit vectors representing the LOE sets for call points for functions are stored in an LOE table indexed or hashed by call graph edges. For each function definition reached in the call graph traversal, a LOE set for the function itself is generated by taking the union of the LOE call point sets. The entries in the LOE table for the LOE call point sets are then removed. The LOE set for each function is used to determine if variables that are the subject of a store operation in a function may be subject to a dead store elimination optimization.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventor: Roch Georges Archambault
  • Patent number: 6651246
    Abstract: Loop allocation for optimizing compilers includes the generation of a program dependence graph for a source code segment. Control dependence graph representations of the nested loops, from innermost to outermost, are generated and data dependence graph representations are generated for each level of nested loop as constrained by the control dependence graph. An interference graph is generated with the nodes of the data dependence graph. Weights are generated for the edges of the interference graph reflecting the affinity between statements represented by the nodes joined by the edges. Nodes in the interference graph are given weights reflecting resource usage by the statements associated with the nodes. The interference graph is partitioned using a profitability test based on the weights of edges and nodes and on a correctness test based on the reachability of nodes in the data dependence graph. Code is emitted based on the partitioned interference graph.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Roch Georges Archambault, Robert James Blainey
  • Publication number: 20030115579
    Abstract: An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operatively coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to store a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 19, 2003
    Applicant: International Business Machines Corporation
    Inventors: Roch Georges Archambault, Robert James Blainey, Charles Brian Hall, Yingwei Zhang
  • Publication number: 20020095669
    Abstract: A system for optimizing computer code generation by carrying out interprocedural dead store elimination. The system carries out a top down traversal of a call graph in an intermediate representation of the code being compiled. Live on exit (LOE) sets are defined for variables at call points for functions in the code being compiled. Bit vectors representing the LOE sets for call points for functions are stored in an LOE table indexed or hashed by call graph edges. For each function definition reached in the call graph traversal, a LOE set for the function itself is generated by taking the union of the LOE call point sets. The entries in the LOE table for the LOE call point sets are then removed. The LOE set for each function is used to determine if variables that are the subject of a store operation in a function may be subject to a dead store elimination optimization.
    Type: Application
    Filed: September 27, 2001
    Publication date: July 18, 2002
    Inventor: Roch Georges Archambault
  • Publication number: 20020095667
    Abstract: An optimizing compiler includes a component for the determination of potential forward movements of store operations in the compilation of the computer software code. An intermediate representation of computer code is generated including a control flow graph, a data flow graph, a dominator tree, and a reaching defs table. These data structures are accessed to determine where in a conditional branch of code a store operation in the code may be moved to potentially increase efficiency in the execution of the compiled code. Tree structures corresponding to store operations are identified for possible movement, either entirely, or partially. Where a movement of a part of a tree structure is identified, temporary registers may be used to retain values of variables to enable the move to be carried out.
    Type: Application
    Filed: September 27, 2001
    Publication date: July 18, 2002
    Inventor: Roch Georges Archambault