Patents by Inventor George Arthur Rozgonyi

George Arthur Rozgonyi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 3997368
    Abstract: Described are procedures for fabricating silicon devices which prevent the formation and/or activation of stacking fault nucleation sites during high temperature processing steps, such as steam oxidation of silicon wafers. The procedures, which take place before such high temperature steps, include forming on the back surface of the wafer a stressed layer and then annealing the wafer for a time and at a temperature effective to cause the nucleation sites to diffuse to a localized region near to the back surface. Illustratively the stressed layer comprises silicon nitride or aluminum oxide. Enhanced gettering is achieved if, prior to forming the stressed layer, interfacial misfit dislocations are introduced into the back surface by, for example, diffusion of phosphorus therein. Following the gettering step(s) on the back surface, conventional procedures, such as growing epilayers and/or forming p-n junctions, are performed on the front surface of the wafer.
    Type: Grant
    Filed: June 24, 1975
    Date of Patent: December 14, 1976
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Pierre Marc Petroff, George Arthur Rozgonyi
  • Patent number: 3962716
    Abstract: Described is a procedure for virtually eliminating disclocations in multilayer structures of materials having a crystallographic zinc-blend structure, in particular quaternary layers of Al.sub.y Ga.sub.1.sub.-y As.sub.1.sub.-z P.sub.z grown on Al.sub.x Ga.sub.1.sub.-x As substrates (y > x .gtoreq. 0). By carefully controlling the quaternary layer thickness and the lattice parameter mismatch at the growth temperature, it is possible to change the direction of substrate dislocations as they enter the substrate/layer interface. The length of the dislocation in the interfacial plane can be extended so that it is "infinitely" long, i.e., it reaches the edge of the wafer. As a result, the epitaxial quaternary layer and all layers subsequently grown thereon will be virtually dislocation free, provided that the thickness, stress and uniformity of the layers are such that no surface dislocation souces are activated.
    Type: Grant
    Filed: April 25, 1974
    Date of Patent: June 8, 1976
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Pierre Marc Petroff, George Arthur Rozgonyi
  • Patent number: 3958263
    Abstract: The average stress between contiguous layers of Al.sub.x Ga.sub.1.sub.-x As and Al.sub.y Ga.sub.1.sub.-y As (y > x) is reduced by the addition of phosphorus during the growth of the latter layer to produce the quaternary Al.sub.y Ga.sub.1.sub.-y As.sub.1.sub.-z P.sub.z instead of the ternary Al.sub.y Ga.sub.1.sub.-y As. In order to reduce the average stress to less than about 2 .times. 10.sup.8 dynes/cm.sup.2 the amount of phosphorus added should satisfy the condition: ##EQU1## Also described is a double heterostructure junction laser comprising a GaAs or AlGaAs active layer sandwiched between layers of AlGaAsP.
    Type: Grant
    Filed: April 25, 1974
    Date of Patent: May 18, 1976
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Morton B. Panish, George Arthur Rozgonyi