Abstract: An electrically configurable decoder including selectively configurable combinations of a plurality of basic decode circuits. The electrically configurable decoder includes a plurality of mode selection inputs, a plurality of address inputs, a plurality of logic level definition inputs, and a plurality of disable inputs. Various combinations of decoding functions are provided by the electrically configurable decoder in response to the mode selection inputs. A plurality of selection circuits selectively decodes various ones of the address inputs and mode selection inputs to produce signals which are applied to decode inputs and enable inputs of the basic decoder circuits. A logical "one" applied to a first one of the logic level definition inputs causes "high" and "low" voltage levels produced at the outputs of a first one of the basic decoder circuits to represent logical "ones" and "zeroes," respectively.

Abstract: A microprogrammed processor having a bit-addressable scratch pad memory with variable length operands and a method of operation which increase processor operating speed, permit use of simpler interpretive firmware, and require a reduced amount of firmware memory than prior microprogrammed processors. Microinstructions each including a six bit op code field and first and second five bit address fields are stored in a high speed firmware memory. The two address fields are transferred to address inputs of a dual port descriptor memory which stores descriptors. Two descriptors are simultaneously fetched from locations of the descriptor memory determined by the first and second address fields of the microinstruction. Each descriptor includes an address field which defines a location of the least significant bit of an operand in the scratch pad memory and a length field which defines the length of that operand.

Abstract: The clocked flip-flop circuit of the present invention is one that cannot be caused to yield an erroneous output upon a skew in a clock pulse or, equivalently, the offset of such pulse with respect to its complement. The disclosed flip-flop circuit is comprised of a J-K master portion and a D latch slave portion. Each portion includes a gate having no operative functional definition as respects provision of an output under normal operating conditions of the circuit. In normal operation, the circuit, exclusive of the additional gates, provides HOLD, SET/RESET and TOGGLE functions according as the setting of J and K inputs. Upon skew of a clock pulse, the additionally provided gates insure integrity of the outputs corresponding to the J and K settings by defining a failure mode of operation of the flip-flop, independent of the clock.