Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: Low-k dielectric materials are incorporated as an insulator material between bit lines and an inter-level dielectric material. The device is first processed in a known manner, up to and including the deposition and anneal of the bit line metal, using a higher dielectric constant material that can withstand the higher temperature process steps as the insulator between the bit lines. Then, the higher dielectric constant material is removed using an etch that is selective to the bit line metal, and the low-k dielectric material is deposited. The low-k material may then be planarized to the top of the bit lines, and further low-k material deposited as an inter-level dielectric. Alternatively, sufficient low-k material is deposited in a single step to both fill the gaps between the bit lines as well as serve as an inter-level dielectric, and then the low-k dielectric material is planarized. Standard processing may then be carried out.

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: A method and structure for an integrated circuit transistor structure includes a gate conductor that has a first conductive material and a second material. The invention has non-deformable spacers adjacent the gate conductor and a gap between the gate conductor and the spacer. The first conductive material can be polysilicon and the second material can be either a metal or a polymer. The second material acts as a placeholder for the gap. In the invention, the gap holds ambient gas and decreases resistance of the gate conductor.

Abstract: A synchronous dynamic random access memory subsystem includes two banks of connectors for receiving single or dual in-line memory modules. A clock is located in close proximity to the connectors and produces clock pulses having a known rise time. Clock wiring is placed between the clock and the connectors, and module wiring carries the clock pulses from the connectors to the memory. The wiring has an impedance and length such that the round trip delay time of clock pulses between the clock and the memory is less than the rise time of the clock pulses. The clock is preferably located between the two banks of connectors to reduce wiring length to a minimum and minimize coupled noise.

Abstract: Multiple synchronous dynamic random access memories (SDRAMs) are packaged in a single or a dual in-line memory module to have similar physical and architectural characteristics of dynamic random access memories (DRAMs) packaged in single/dual in-line memory modules. A 168 pin SDRAM DIMM family is presented which requires no modification of existing connector, planar or memory controller components. The 168 pin SDRAM DIMM family includes 64 bit non-parity, 72 bit parity, 72 bit ECC and 80 bit ECC memory organizations. Special placement and wiring of decoupling capacitors about the SDRAMs and the buffer chips contained within the module are also presented to reduce simultaneous switching noises during read and write operations. A special wiring scheme for the decoupling capacitors is employed to reduce wiring inductance.

Abstract: An electronic component package, including: a multilayer ceramic or glass-ceramic substrate formed of a stacked plurality of generally parallel signal and insulating layers, each of the signal layers comprising an electrically conductive pattern; a cavity in a surface of the substrate sized to accommodate an electronic component with a planar surface of the electronic component disposed substantially planar with the surface of the substrate; and a plurality of electrical conductors extending from the surface of the substrate to selected ones of the signal layers for connecting the electronic component to the signal layers. Thin film wiring is provided for connecting the electronic component to the substrate.

Abstract: A resist mark comprising two layers of resist, one of which is saturated with a diluant which does not dissolve the other. In one embodiment, the two layers of resist are applied upon a substrate, the first layer of which is more soluble in a developer. The second layer is said saturated resist and the first layer is non-saturated. This composite is preferably used to form a relief mask with recessed sidewalls used in lift-off processes.

Abstract: A resist mask comprising two layers of resist, one of which is saturated with a dilutant which does not dissolve the other. In one embodiment, the two layers of resist are applied upon a substrate, the first layer of which is more soluble in a developer. The second layer is said saturated resist and the first layer is non-saturated. This composite is preferably used to form a relief mask with recessed sidewalls used in lift-off processes.

Abstract: A resist mask comprising two layers of resist, one of which is saturated with a dilutant which does not dissolve the other. In one embodiment, the two layers of resist are applied upon a substrate, the first layer of which is more soluble in a developer. The second layer is said saturated resist and the first layer is non-saturated. This composite is preferaly used to form a relief mask with recessed sidewalls used in lift-off processes.

Abstract: A method of forming extremely small impurity regions within other impurity regions without the need for providing critical masks. In the preferred embodiment this is achieved by forming an undercut band within masking layers atop a substrate to define a first impurity region, such as the base region of a bipolar transistor. After this region is formed by the introduction of impurities, the undercut is filled-in by a chemical vapor deposition process. A blocking mask may then be used for the formation of the second impurity region, in this case the emitter, within the first region. The window of the second region is defined by the filled-in band, thereby insuring a selected distance between the peripheries of said first and second impurity regions. The same mask may also be used to form other self-aligned regions with the first region.