Abstract: The circuit and structure of a direct write differential nonvolatile memory cell. The features of the cell include high speed read sensing, write without a prior erase operation, single polysilicon fabrication capability, and memory margining capabilities. The structural and functional symmetry maximizes cell density while providing complementary differential operation. In a preferred arrangement, the cell utilizes a pair of cross-coupled, capacitively complementary, centrally disposed floating gate electrodes. The cell is written directly by the provision of complementary signals on a pair of program lines, which lines are capacitively coupled to the floating gate electrodes. The data state of the cell is sensed by conduction in two bit lines, the conductive states of the lines being determined by the charge transferred onto the two floating gate electrodes during the simultaneous but complementary programming of such electrodes.

Abstract: A floating gate type nonvolatile memory cell of the general class known as electrically erasable programmable read only memories, configured with a single polysilicon layer, operable in a direct write mode, and characterized by its absence of read disturb. In one form of its practice, the floating gate is divided into three regions situated with relation to specified regions in the substrate. The first region of the floating gate is dielectrically isolated from a conductively doped region in the substrate so as to form a capacitor; the second region is similarly situated, but forms a significantly smaller capacitor and utilizes a dielectric suitable for Fowler-Nordheim tunneling or Poole-Frenkel conduction of charge therethrough; and the third region overlaps a channel of a field effect type sense transistor, conduction through which is responsive to the charge resident on the floating gate.

Abstract: An EEPROM cell which is programmed to a 1 or .0. binary state regardless of the prior state of the cell, that is, without erasing. The cell construction includes silicon nitride capacitors between the floating gate and the programming electrodes which enhances the programming characteristics and the endurance and permits the use of a relatively simple double layer polysilicon process and semiconductor structure.

Abstract: A signal generator for producing, from a low voltage power supply, relatively large magnitude pulse signals of opposite polarity to a device input terminal having a parallel resistor-capacitor circuit connection to a reference voltage. A voltage multiplier powered by the low voltage power supply provides a multiplied voltage output which is stored on a first large capacitor. A second large capacitor has one terminal connected to the device input terminal. To produce the large, opposite polarity signals, a control circuit means operates in conjunction with the voltage multiplier and the first capacitor to produce a predetermined sequence of voltages on the second terminal of the second capacitor.

Abstract: A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line.

Abstract: A low voltage write, avalanche breakdown, nonvolatile MNOSFET memory device. The device is preferably an n-channel enhancement mode, split-gate or trigate structure having a first, relatively highly doped p+ channel region and a second, underlying p-region. The p+ region is coextensive with the thin, memory oxide structure. The binary state of the device is selected by applying a low voltage (e.g., +12v) to the gate and simultaneously applying a suitable voltage to the source and/or drain to induce avalanche breakdown in the channel, or not, to write the device to a "1" state or maintain the device in its original "0" state.

Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section and an alterable section, the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes. The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.

Abstract: A novel memory array is disclosed, the array utilizing a matrix of variable threshold insulated gate field effect transistor cells. The cells are comprised solely of a gate region, having nitride and oxide layers, and a source region with the output data sensed, at the source, as a change of source charge as distinguished from the prior art sensing of a change of low impedance source voltage. In operation, each cell functions as an alterable capacitor. A negative pulse applied to the gate selects the cell. Variations in stored charge at the nitride-oxide interface causes changes in the threshold voltage and effective capacitance of the cell. The source charge may then be sensed to read the stored data.

Abstract: An improved one shot multivibrator circuit is described which is particularly adapted for use with field-effect transistor (FET) manufacturing techniques such as metal oxide semiconductor (MOS) large scale integration (LSI) manufacturing techniques. Such a one shot multivibrator circuit is particularly adapted for FET application because the period of its output pulse is independent of the threshold voltages of the transistors used in the circuit design. The one shot multivibrator circuit comprises a capacitor for fixing the period of the output pulse; a bias network including a current mirror as a constant current source for charging the capacitor; a first inverter stage comprising a switching transistor and a load transistor for controlling the charging and discharging of the capacitor; and a second inverter stage as the output stage for providing the output pulse having its turn-on controlled by the first inverter stage and its turn-off controlled by the voltage level on the capacitor.

Abstract: A high speed field-effect transistor (FET) bistable multivibrator circuit is described. This bistable circuit employs two stable states and comprises a first section and a second section. Each section comprises a load transistor of high resistance magnitude for insuring a high gain; input means for storing a voltage representation of the input signal applied to that section; switching means responsive to the voltage stored in the input means for turning on one of the switching transistors; and cross-coupling and driving means, responsive to the switching transistor which turns on, for discharging the voltage representation of the input signal applied to the switching transistor in the opposite section.