Patents by Inventor George C. Wellwood
George C. Wellwood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9513993Abstract: Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.Type: GrantFiled: September 30, 2014Date of Patent: December 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luis A. Lastras, Patrick J. Meaney, Eldee Stephens, George C. Wellwood
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Patent number: 9437327Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: GrantFiled: March 8, 2016Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
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Publication number: 20160172055Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: ApplicationFiled: March 8, 2016Publication date: June 16, 2016Inventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
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Patent number: 9298614Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: GrantFiled: March 14, 2014Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
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Patent number: 9189330Abstract: Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.Type: GrantFiled: April 11, 2013Date of Patent: November 17, 2015Assignee: International Business Machines CorporationInventors: Luis A. Lastras, Patrick J. Meaney, Eldee Stephens, George C. Wellwood
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Publication number: 20150262706Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
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Publication number: 20150019905Abstract: Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Luis A. Lastras, Patrick J. Meaney, Eldee Stephens, George C. Wellwood
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Publication number: 20140310570Abstract: Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Applicant: International Business Machines CorporationInventors: Luis A. Lastras, Patrick J. Meaney, Eldee Stephens, George C. Wellwood
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Patent number: 7900079Abstract: A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced store operations. The self test function then generates fetch commands to read back the unique data patterns from the two DRAM addresses. In the fetch operations, the data transmission for each operation and between both operations is contiguous (no gaps). A self test data comparison function is then used to compare these fetched data words to data patterns which are generated from the self test data generator. Bit error counters from the memory controller keeps track of any miscompares. By reading out a unique signature from these bit counters, it can be determined whether the store path data are misaligned early or late or correct and/or the fetch path data are misaligned early or late or correct. In addition, the exact number of cycles the data are early or late is known.Type: GrantFiled: August 11, 2006Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Kenneth Y. Chan, Kevin W. Kark, George C. Wellwood
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Publication number: 20080126664Abstract: A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced store operations. The self test function then generates fetch commands to read back the unique data patterns from the two DRAM addresses. In the fetch operations, the data transmission for each operation and between both operations is contiguous (no gaps). A self test data comparison function is then used to compare these fetched data words to data patterns which are generated from the self test data generator. Bit error counters from the memory controller keeps track of any miscompares. By reading out a unique signature from these bit counters, it can be determined whether the store path data are misaligned early or late or correct and/or the fetch path data are misaligned early or late or correct. In addition, the exact number of cycles the data are early or late is known.Type: ApplicationFiled: August 11, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenneth Y. Chan, Kevin W. Kark, George C. Wellwood
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Publication number: 20070283104Abstract: Disclosed are a concurrent selftest engine and its applications to verify, initialize and scramble the system memory concurrently along with mainline operations. In prior art, memory reconfiguration and initialization can only be done by firmware with a full system shutdown and reboot. The disclosed hardware, working along with firmware, allows us to do comprehensive memory test operations on the extended customer memory area while the customer mainline memory accesses arc running in parallel. The hardware consists of concurrent selftest engines and priority logic. Great flexibility is achieved by the new design because customer-usable memory area can be dynamically allocated, verified and initialized. The system performance is improved by the fact that the selftest is hardware-driven whereas in prior art, the firmware drove the selftest. More comprehensive test patterns can be used to improve system memory RAS as well.Type: ApplicationFiled: May 31, 2006Publication date: December 6, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: George C. Wellwood, Liyong Wang, Kevin W. Kark
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Patent number: 7100004Abstract: Memory is scrubbed by an improved non-linear method giving scrubbing preference to the central storage region having the characteristic of a high risk read-only memory such as the CPA region to prevent the accumulation of temporary data errors. The chip row on which the CPA resides is scrubbed after each time the scrubbing of a non-CPA chip row in a PMA completed successfully. The next non-CPA least recently scrubbed chip row would be selected for scrubbing after scrubbing completed on the CPA chip row. This in a first case provides non-linear selection methods of scrubbing central storage of computer systems to more frequently select (“select” herein encompasses the meaning of “favor”) scrub regions having the characteristic of a predominately read-only memory making those regions at a higher risk of failure than those regions having lower risk because of frequent write operations.Type: GrantFiled: April 6, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Judy S. Chen Johnson, Kevin W. Kark, George C. Wellwood
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Patent number: 6052772Abstract: A memory request protocol allows a memory request to be withdrawn or "cancelled" without penalty so no memory resource is wasted in doing so during an assigned "cancel window". When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or "cancel window".Type: GrantFiled: April 13, 1998Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventors: Kevin W. Kark, William Wu Shen, George C. Wellwood
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Patent number: 5267242Abstract: A computer memory maintainence apparatus tests operating system storage and identifies a malfunctioning memory chip in an on-line memory array by detecting and recording all permanent data errors using data comparison along with data complementation and substitutes a spare memory chip for the malfunctioning one for all memory read commands. All write commands are performed on both spare memory and the malfunctioning memory chip. All contents of defective chip are copied to the spare chip. The computer system maintains the scrubbing and a recording counter for each of the data bits in an ECC memory data word. The sparing logic in the memory storage system maintains the bit steering logic and controls for the spare chip. When a counter is incremented above a threshold sparing is invoked to replace the failing bit position. The system writes to the defective and spare chips in parallel even after bit steering is invoked.Type: GrantFiled: September 5, 1991Date of Patent: November 30, 1993Assignee: International Business Machines CorporationInventors: Russell W. Lavallee, Donald G. O'Brien, Michael Rubino, William W. Shen, George C. Wellwood