Patents by Inventor George Chamberlain
George Chamberlain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7511754Abstract: Many electrical sensing devices include an array of transducer elements for converting external stimuli to electrical indications. Novel technologies to realize improvements in low power consumption, low noise, and analog output path which occupies minimal die area while maintaining certain data rates are disclosed. A two stage pipeline architecture of the invention in the analog output path maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.Type: GrantFiled: October 26, 2004Date of Patent: March 31, 2009Assignee: Harusaki Technologies, LLCInventors: John Scott-Thomas, Paul Hua, George Chamberlain
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Patent number: 7383425Abstract: This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.Type: GrantFiled: February 27, 2004Date of Patent: June 3, 2008Assignee: Pleora Technologies Inc.Inventors: Eric Boisvert, Alain Rivard, George Chamberlain
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Publication number: 20050088554Abstract: Many electrical sensing devices include an array of transducer elements for converting external stimuli to electrical indications. Novel technologies to realize improvements in low power consumption, low noise, and analog output path which occupies minimal die area while maintaining certain data rates are disclosed. A two stage pipeline architecture of the invention in the analog output path maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.Type: ApplicationFiled: October 26, 2004Publication date: April 28, 2005Inventors: John Scott-Thomas, Paul Hua, George Chamberlain
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Publication number: 20050086352Abstract: This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.Type: ApplicationFiled: February 27, 2004Publication date: April 21, 2005Inventors: Eric Boisvert, Alain Rivard, George Chamberlain
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Publication number: 20050068951Abstract: This invention relates in general to data communications, and in particular, to the delivery of video over a data network. It discloses a communications protocol for use with high performance imaging systems networks providing multi-point-to-multi-point connection between the video sources and the receiving host. The protocol is useful for imaging systems that deliver all the video information reliability in real time to the receiving host.Type: ApplicationFiled: February 27, 2004Publication date: March 31, 2005Inventors: Alain Rivard, Eric Boisvert, George Chamberlain
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Patent number: 6831690Abstract: Many electrical sensing devices include an array of transducer elements for converting external stimuli to electrical indications. Novel technologies to realize improvements in low power consumption, low noise, and analog output path which occupies minimal die area while maintaining certain data rates are disclosed. A two stage pipeline architecture of the invention in the analog output path maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.Type: GrantFiled: December 7, 1999Date of Patent: December 14, 2004Assignee: Symagery Microsystems, Inc.Inventors: Scott-Thomas John, Paul Hua, George Chamberlain
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Patent number: 6489798Abstract: A method and apparatus for testing an image sensor array such as a C-MOS imager which has sensing circuits arranged in rows and columns and wherein the sensing circuits include photosensitive devices is described. A reset voltage is applied to the photosensitive device in each of the sensor circuits such that at least adjacent circuits are reset to different voltage levels. The voltage on each photosensitive device is detected and compared to an expected level to determine if and where any faults may exist in the sensing circuits or lines in the array. A different reset voltage may be applied to each of the sensor circuits, however in one embodiment, a supply with only two voltage levels may be used. One voltage level is applied to every second column to provide a supply voltage to the photosensitive devices and to every second row to generate a reset enable signal for the photosensitive devices.Type: GrantFiled: March 30, 2000Date of Patent: December 3, 2002Assignee: Symagery Microsystems Inc.Inventors: John Scott-Thomas, Ron McDonald, Tom Little, George Chamberlain
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Patent number: 6289116Abstract: A method for extracting design information from a semiconductor integrated circuit (IC) or at least a portion thereof comprising the steps of: (a) imaging at least a portion of one or more IC layers to obtain stored images of said portions of the IC; (b) using manual or automatic registration techniques to mosaic images; (c) using an IC layout package possessing a feature of allowing images to be displayed and moved and polygons to be created to allow the recreation of the IC layout in the form of polygons; (d) exporting or storing of a polygon database in a standard IC layout format; (e) creating a table of transistor connections (netlist); (f) organizing circuit netlist into functional blocks of increasing complexity; and (g) generating a schematic diagram.Type: GrantFiled: September 26, 1997Date of Patent: September 11, 2001Assignee: Semiconductor Insights, Inc.Inventors: George Chamberlain, Larry Lam
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Patent number: 6236746Abstract: A method for analyzing an integrated circuit (IC). At least a portion of a layer of the IC is scanned using high magnification, to obtain images of the IC. The images are registered to create a mosaicked image. An IC layout database is created in the form of a set of polygons from the mosaicked image, where the step of creating the IC layout database is performed after, or pipelined with, the registering step. The process is repeated for plural IC layers, as necessary. Polygon sets from each layer are vertically registered into alignment with minimal distortion. A netlist or schematic diagram is generated to represent the scanned IC portion based on the registered set(s) of polygons.Type: GrantFiled: October 1, 1997Date of Patent: May 22, 2001Assignee: Semiconductor Insights, Inc.Inventors: George Chamberlain, Alexi Ioudovski, John-Scott Thomas, Ghassan Naim
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Patent number: 5788564Abstract: An apparatus for anesthetizing animals for slaughter has a gas chamber with an inlet at one end and an outlet at another end, and an inclined inlet ramp extending to the inlet of the chamber and a declined outlet chute for receiving anesthetized animals from the outlet of the chamber. The inlet ramp is sized to force the animals to proceed to the inlet in single file. A continuous belly conveyor extends through the gas chamber from the inlet, through an anesthetizing gas zone, and through the outlet for supporting the animals on their bellies and transporting them through the gas chamber in single file at a rate sufficiently slow to ensure each animal is rendered unconscious by the time it reaches the outlet. The conveyor has a pickup portion extending from the inlet of the chamber into the inlet ramp for receiving individual animals and supporting them on their bellies for introduction into the chamber.Type: GrantFiled: October 16, 1996Date of Patent: August 4, 1998Assignee: Maple Leaf Pork, A Division of Maple Leaf MeatsInventor: George Chamberlain
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Patent number: 5694481Abstract: A method of analyzing at least a portion of an integrated circuit (IC) comprised of the steps of automatically: (a) scanning at least a portion of a layer of an integrated circuit using high magnification to provide first digital signals representing pixel amplitudes, (b) extracting features of interest from the first digital signals to provide second digital signals representing values of groups of pixels defining the features of interest, (c) modifying the second digital signals representing adjacent features of interest from step (b) so as to mosaic the features of interest and providing third signals representing a seamless representation of the layer, (d) repeating steps (a), (b) and (c) for other layers of the integrated circuit, whereby plural third signals representing plural ones of the layers are provided, (e) registering the plural third signals relative to each other so as to represent vertical alignment of the layers by determining features of interest representative of IC mutual interconnectionType: GrantFiled: April 12, 1995Date of Patent: December 2, 1997Assignee: Semiconductor Insights Inc.Inventors: Larry Lam, George Chamberlain, Alexei Ioudovsky, Ghassan Naim
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Patent number: 3974984Abstract: 1.Type: GrantFiled: March 23, 1962Date of Patent: August 17, 1976Assignee: British Aircraft CorporationInventors: Geoffrey Townsend Dobson, Sidney George Chamberlain