Abstract: In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

Abstract: A head-mountable display device includes a housing defining a front opening and a rear opening, a display screen disposed in the front opening, a display assembly disposed in the rear opening, a first securement strap coupled to the housing, the first securement strap including a first electronic component, a second securement strap coupled to the housing, the second securement strap including a second electronic component, and a securement band extending between and coupled to the first securement strap and the second securement strap.

Abstract: Methods, systems, and media for determining and presenting information related to embedded sound recordings are provided.

Abstract: A battery safety system includes a flow valve and a sensing device. The flow valve is disposed on a housing of the battery and includes a first valve that is embedded inside the housing and a second valve that intersects the housing. The first valve includes a cavity through which analytes released upon electrochemical reactions within the battery flow towards the second valve. The second valve extends through the housing to the outside, and defines an opening through which the released analytes exit the housing. The sensing device is disposed within the cavity of the first valve of the valve and is situated in a manner to be in fluidic contact with the released analytes as they flow from the inside of the battery to the outside. In some aspects, the battery safety system can detect a minute presence of one or more analytes. In some aspects, the sensor is in communication with a battery management system.

Abstract: This disclosure describes, in part, techniques for sharing content associated with network applications. For instance, a user may want to share content for a network application, such as a game stream for a gaming application. As such, system(s) may launch a broadcasting session on a first virtual server and launch the network application on a second virtual server. The first virtual server may then receive content data representing states of the network application from the second virtual server. Additionally, the first virtual server may receive video data representing the user and/or audio data representing user speech from a user device. The first virtual server may then generate broadcasting data using the content data, the video data, and the audio data. After generating the broadcasting data, the system(s) may send the broadcasting data to one or more computing devices associated with a user account.

Abstract: A venting device includes an anchor structure and a membrane. The membrane is anchored on the anchor structure and configured to form a first vent and a second vent. The membrane includes a first flap, a second flap and a third flap. The membrane partitions a space into a first volume and a second volume, and the first volume and the second volume are connected when the first vent and the second vent are formed. The first flap is actuated to move toward a first direction and the second flap is actuated to move toward a second direction opposite to the first direction, so as to form the first vent. The first flap is actuated to move toward the first direction and the third flap is actuated to move toward the second direction opposite to the first direction, so as to form the second vent.

Abstract: In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

Abstract: A semiconductor device includes a backside contact and a substrate. An epitaxial field stop region may be formed on the substrate with a graded doping profile that decreases with distance away from the substrate, and an epitaxial drift region may be formed adjacent to the epitaxial field stop region. A frontside device may be formed on the epitaxial drift region.

Abstract: In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

Abstract: In some aspects, the techniques described herein relate to a semiconductor device including: a substrate having a first side and a second side, the second side being opposite the first side; active circuitry disposed on the first side of the substrate; a metallic implant disposed in the substrate, the metallic implant being a blanket implant on the second side of the substrate; and a metallic layer disposed on the second side of the substrate, the metallic layer and the second side of the substrate including the metallic implant defining an ohmic contact.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: A method for singulating a semiconductor wafer includes providing the semiconductor wafer having a plurality of semiconductor devices adjacent to a first surface, the plurality of semiconductor devices separated by spaces corresponding to where singulation lines will be formed. The method includes providing an alignment structure adjacent to the first surface and providing a material on a second surface of the semiconductor wafer, wherein the material is absent on the second surface directly below the alignment structure. The method includes passing an IR signal through the semiconductor wafer from the second surface to the first surface where the material is absent to detect the alignment structure and align a singulation device to the spaces where the singulation lines on will be formed.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.