Patents by Inventor George Cheroff

George Cheroff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7087507
    Abstract: A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by ion implantation. The process of implantation provides precise placement of deuterium at optimum locations within the gate stack to create stable silicon-deuterium bond terminations at the Si—SiO2 interface within the gate-channel region. The deuterium is encapsulated in the MOSFET by the use of a Silicon Nitride (SiN) barrier mask. The ability of deuterium to passivate dangling silicon bonds is maximized by removing hydrogen present in the MOSFET and by use of an absorption layer to create a deuterium rich region.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: August 8, 2006
    Assignee: PDF Solutions, Inc.
    Inventors: Viktor Koldiaev, Jeff Babock, George Cheroff
  • Publication number: 20050255684
    Abstract: A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by ion implantation. The process of implantation provides precise placement of deuterium at optimum locations within the gate stack to create stable silicon-deuterium bond terminations at the Si—SiO2 interface within the gate-channel region. The deuterium is encapsulated in the MOSFET by the use of a Silicon Nitride (SiN) barrier mask. The ability of deuterium to passivate dangling silicon bonds is maximized by removing hydrogen present in the MOSFET and by use of an absorption layer to create a deuterium rich region.
    Type: Application
    Filed: May 17, 2004
    Publication date: November 17, 2005
    Inventors: Viktor Koldiaev, Jeff Babock, George Cheroff
  • Publication number: 20050040479
    Abstract: A spacer (2) for a MOSFET is provided with an Oxide-Nitride-Oxide structure. The nitride layer (18) has a structure formed through a process that isolates first oxide layer (16) from ammonium precursors that may be used to form nitride layer (18).
    Type: Application
    Filed: August 20, 2003
    Publication date: February 24, 2005
    Inventors: Viktor Koldiaev, George Cheroff