Patents by Inventor George Chrysos

George Chrysos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060045120
    Abstract: A method and apparatus for preventing starvation in a slotted-ring network. Embodiments may include a ring interconnect to transmit bits, with one of the bits being a slot reservation bit, and nodes coupled to the ring interconnect, with each node comprising a starvation detection element and a slot reservation element to reserve a slot for future use. In further embodiments, each node may also comprise a slot tracking element to track the location of the slot reserved by that node.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Matthew Mattina, George Chrysos, Yungho Choi
  • Publication number: 20060041715
    Abstract: Embodiments of the present invention are related in general to on-chip integration of multiple components on a single die and in particular to on-chip integration of multiple processors via a bidirectional ring interconnect. An embodiment of a semiconductor chip includes a plurality of processors, an address space shared between the processors, and a bidirectional ring interconnect to couple the processors and the address space. An embodiment of a method includes calculating distances between a packet source and destination on multiple ring interconnects, determining on which interconnect to transport the packet, and then transporting the packet on the determined interconnect. Embodiments provide improved latency and bandwidth in a multiprocessor chip. Exemplary applications include chip multiprocessing.
    Type: Application
    Filed: May 28, 2004
    Publication date: February 23, 2006
    Inventors: George Chrysos, Matthew Mattina, Stephen Felix
  • Publication number: 20060026371
    Abstract: In one embodiment of the present invention, a method includes generating a first order vector corresponding to a first entry in an operation order queue that corresponds to a first memory operation, and preventing a subsequent memory operation from completing until the first memory operation completes. In such a method, the operation order queue may be a load queue or a store queue, for example. Similarly, an order vector may be generated for an entry of a first operation order queue based on entries in a second operation order queue. Further, such an entry may include a field to identify an entry in the second operation order queue. A merge buffer may be coupled to the first operation order queue and produce a signal when all prior writes become visible.
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Inventors: George Chrysos, Ugonna Echeruo, Chyi-Chang Miao, James Vash
  • Publication number: 20060005082
    Abstract: A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.
    Type: Application
    Filed: July 2, 2004
    Publication date: January 5, 2006
    Inventors: Tryggve Fossum, George Chrysos, Todd Dutton
  • Publication number: 20050276274
    Abstract: Embodiments of the present invention are related in general to data flow control in a network and in particular to synchronous packet flow control in a ring interconnect. An embodiment of a method may include rejecting an arriving packet at a destination node on a semiconductor chip's ring interconnect, e.g., an unbuffered, synchronous ring interconnect, if all of the destination node's buffers are not available, leaving the rejected packet on the ring interconnect to continue traversing the ring, and accepting the rejected packet upon arrival at the destination node, if a buffer is available. In an alternate embodiment, a method may include tracking the rejected packet as the rejected packet traverses the ring interconnect. An embodiment of an apparatus may include a semiconductor chip having a bidirectional ring interconnect and multiple nodes coupled to the bidirectional ring interconnect.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 15, 2005
    Inventors: Matthew Mattina, George Chrysos, Stephen Felix
  • Publication number: 20050144390
    Abstract: The present application is a protocol for maintaining cache coherency in a CMP. The CMP design contains multiple processor cores with each core having it own private cache. In addition, the CMP has a single on-ship shared cache. The processor cores and the shared cache may be connected together with a synchronous, unbuffered bidirectional ring interconnect. In the present protocol, a single INVALIDATEANDACKNOWLEDGE message is sent on the ring to invalidate a particular core and acknowledge a particular core.
    Type: Application
    Filed: December 30, 2003
    Publication date: June 30, 2005
    Inventors: Matthew Mattina, George Chrysos
  • Publication number: 20050144392
    Abstract: A mechanism which allows invalidations several attempts to read the tag array and perform a invalidation. If in a given cycle, an invalidation request conflicts with a fill request, the invalidation request is piped and tried again in the next cycle. After several attempts, the invalidation will give up on trying to read the tag array and just perform invalidation on every block in the indexed set.
    Type: Application
    Filed: December 30, 2003
    Publication date: June 30, 2005
    Inventor: George Chrysos
  • Publication number: 20050027941
    Abstract: Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventors: Hong Wang, Perry Wang, Jeffery Brown, Per Hammarlund, George Chrysos, Doron Orenstein, Steve Liao, John Shen
  • Publication number: 20030126409
    Abstract: A microprocessor embodies a poisoning technique with regard to load and store instructions that are related through a common memory reference. The microprocessor includes “store sets” that are created for loads and stores that share a common memory reference and that must execute in program order. The store sets include a value that points to a poison bit in a store set poison table that indicates whether a store instruction that is part of the store set is poisoned by a load instruction that prior to the store. If the store instruction is poisoned, a subsequent store set related load instruction will also be poisoned. That is, the present technique causes poison to propagate from a parent store to a subsequent memory reference dependent load using a store set.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 3, 2003
    Inventors: Toni Juan, George Chrysos, Chris Gianos, Eric Borch