Abstract: Data can be processed in automatic test equipment by dividing the test sites into groups and processing each group using a corresponding processor in a group of processors. Sections of the test equipment can communicate via a tester bus to a particularly designed multi-stream switch. The multi-stream switch can communicates with a plurality of processors via a plurality of processor busses. Each of the processors can run a separate instance of test software without interfering with software running on any other of the processors. The inventive protocol can be embodied essentially in hardware that can be adapted to an existing infrastructure without requiring substantial modifications of existing hardware or software.

Abstract: A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.

Abstract: A signal interface to connect a semiconductor tester to a device under test. The Interface includes a generic component and customized component. The generic component includes multiple copies of electronic elements that can be connected in signal paths between the tester and the device under test. The customized component is constructed for a specific device under test and provides connections between generic contact points on the generic component and test points on the device under test. In addition, the customized component has conductive members that can be used to interconnect the electronic elements on the generic component. The connections configure the electronic elements into signal conditioning circuitry, thereby providing signal paths through the interface that are compatible with the I/O characteristics of specific test points on a device under test. The generic and the customized components may be fabricated on semiconductor wafers.

Abstract: A test system with easy to fabricate hardware to make measurements on differential signals. The two legs of a differential signal are applied to a comparator. A variable bias is introduced into the comparison operation. By taking multiple measurements with different bias levels, the level of the differential signal may be determined. The time of measurements relative to the start of the signal can be varied to allow plots of the signal to be made. Variability of the signal caused by noise can be measured by collecting sets of data points with the same bias level at the same relative time. Circuitry for introducing bias into the comparison is disclosed that allows measurements to be made with a pre-packaged, commercially available high speed comparator.

Abstract: A channel for use in automatic test equipment and adapted for coupling to a device-under-test is disclosed. The channel includes a driver and respective AC and DC-coupled signal paths. The AC-coupled signal path is disposed at the output of the driver and is configured to propagate signal components at and above a predetermined frequency. The DC-coupled signal path is disposed in parallel with the AC-coupled signal path and is configured to propagate signal components from DC to the predetermined frequency.

Abstract: An automatic test system useful for testing source synchronous devices at high speed. The data outputs of the device under test are routed to channel circuitry within the test system through coaxial cables. The test system includes a buffer amplifier on a device interface board to fan out the DATA CLOCK generated by the device under test to that channel circuitry. The interconnection between the buffer amplifier and the channel circuitry is provided through a coax with low dielectric constant, to compensate for the delay introduced by the buffer amplifier.