Abstract: A memory access approach optimizes memory address mapping for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is directed to a process of accessing data in a plurality of addressable banks of memory cells. The process involves accessing the memory cells by addressing arrays in the banks via column and row bits, and directing the address and control signals so that the addressable column address and row address bits are selected with a lower order group of the address bits directed to select the column address bits, and the next highest group of the address bits directed to select bank address bits. The next highest group of the address bits are directed to select the row address bits.

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc.

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc.

Abstract: A digital-to-analog converter method and apparatus is disclosed which utilizes a hybrid technique of combined pulse width and pulse rate modulation to achieve improved performance with reduced logic and circuitry requirements. Lower order bits of an N-bit digital data input for conversion to a corresponding analog output voltage level are treated in a manner similar to pulse rate modulation approaches utilized previously. High order bits are handled together in a variant form of pulse width (duration) modulation in which the pulse width required to generate the given analog voltage level corresponding to the high order digital bit inputs is divided into a fixed number of slices in a given sample time, each slice having a width or duration of pulse output which is variable in itself in correspondence to a function of both the high and low order bit value inputs. A low pass filter or integrator combines all of the pulses in a given sample to produce the analog voltage level output.