Patents by Inventor George D. Lane

George D. Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 3947956
    Abstract: A method and process of screening multilayer thick-film structures to produce complex hybrid electronic circuits. After deposition, drying and firing of the first conductor plane on the substrate, registration ink is deposited and allowed to dry thus forming temporary vias. A suitable dielectric paste is then deposited either on all the surface or except on viaslocations. The dielectric paste is then dried and fired. Firing however causes sublimation or evaporation of the temporary vias pattern leaving cavities in the dielectric layer. Slight buffing may be required to uncover the via holes. The vias and the second conductor plane are then deposited, dried and fired. The same steps are carried out for each subsequent conductor plane.
    Type: Grant
    Filed: July 3, 1974
    Date of Patent: April 6, 1976
    Assignee: The University of Sherbrooke
    Inventors: Adrien Leroux, Alexandre Kocsis, George D. Lane