Abstract: Arrangements are disclosed for maintaining time synchronization of simulcast radio frequency communications system transmissions. A circuit continually instructs a modem to use the common system clocking signal, and modems are retrained whenever a channel is taken out of service because of a test call failure.

Abstract: In a multiple site radio frequency simulcasting RF transmission system, data transmitted from a control point to the RF transmitter sites exhibits random time delay skew because multi-phase modems recover clock signals from an arbitrary one of the multiple phases. The outputs of the modems are temporarily stored at the sites by memory buffers. The control point derives resynchronization signals from a source data clock, this signal containing frequency and timing information. The resynchronization signal is distributed to the various sites via additional phase-stable, delay compensated channels. Each site is provided with a clock recovery circuit that recovers the original source data clocking signal from the resynchronization signal and also extracts read-out timing information from the resynchronization signal.

Abstract: In a multisite radio frequency simulcasting transmission system involving microwave-multiplex distribution paths to several transmitting sites, each path including manually settable amplitude and time delay devices for equalization of the modulation in signal overlap areas among the various transmitter sites, an automatic simulcast alignment device is included in each distribution path whereby transmissions between a control point and each site transmitter are periodically tested and each path is compensated for amplitude and time delay variations to thus maintain equalized amplitude and time of arrival of the modulation in the transmitter site overlap areas. Thus, the instantaneous distribution of the FM modulation sidebands is maintained to be ideally identical in the signal overlap areas.

Abstract: A memory device is provided for an integrated injection logic (I.sup.2 L) device in solid state form by a resistor connected at one end to the logic device, and a diode having its cathode connected to the other end of the resistor at a programming junction, and its anode connected to a common point. If the diode conductors are melted or deformed by reverse diode current from the programming junction to the common point, a low impedance path is formed, and the logic portion is provided with a first logic input. If the diode conductors are left unmelted or intact, the logic portion is provided with a second logic input.