Abstract: A translation circuit for mixed logic voltage signals is comprised of a first pair of self-biasing common-mode level shifters for receiving positive and negative polarity input signals respectively of a balanced input signal, each level shifter having a control input for receiving a ratio control signal, and having first level shifter nodes for providing the same polarity output signals, a second pair of self-biasing common-mode level shifters, each connected in parallel with a corresponding variable ratio level shifter, the second pair of level shifters having fixed level shift ratios, a circuit connected to level shifter nodes of the second pair of level shifters for providing and storing a signal which is a sum of voltages appearing at the level shifter nodes, and a circuit for applying the stored signal to the control inputs.

Abstract: An integrated circuit output driver which reduces the effect of power supply and/or integrated circuit fabrication process variations on signal propagation delay. The output driver produces an output signal V.sub.out as an increased drive strength replica of an input signal V.sub.in. A pre-driver receives V.sub.in and produces an intermediate, inverted replica V.sub.int thereof. A driver is electrically connected to the pre-driver's output to receive V.sub.int. V.sub.out appears at the driver's output as an inverted, strengthened replica of V.sub.int. A first feedback circuit electrically connected between the driver's input and output applies a pull-down signal to the driver's input in response to a falling edge of V.sub.in, with the pull-down signal's strength varying in inverse proportion to propagation delay of the falling edge of V.sub.in.