Patents by Inventor George Diedrich GRISTEDE

George Diedrich GRISTEDE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230315529
    Abstract: Controlling compute process access to shared data and compute resources includes, responsive to a compute process determining that access to at least one of shared resources and shared data is necessary to perform a compute task, creating, by the compute process, a ticket file belonging to the compute process in a ticket queue directory. The compute process is allowed to proceed performing the compute task upon determining that the ticket file is first in line in a ticket queue of the ticket queue directory, according to a ticket ordering algorithm independently applied by the compute process. Subsequent to completing the compute task, the compute process removes the ticket from the ticket queue directory.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: George Diedrich GRISTEDE, Matthew Mantell ZIEGLER
  • Patent number: 10296691
    Abstract: Disclosed is a system, computer program product, and method for performing logic, physical synthesis, and post-route optimization. The method begins with identifying a plurality of groups of paths in a circuit by a unique criteria. The unique criteria is any one of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof. An optimization process is performed on the design and is repeated until the cumulative histogram corresponds to the reference histogram within a threshold. The histogram optimization on the group of paths to make the cumulative histogram correspond to the reference cumulative histogram can be adjusted to account for timing, power, yield, or a combination thereof. After a first group of paths has been optimized, the process can be repeated for other groups of paths. The histogram optimization performed on each group of paths is merged into overall histogram optimization design.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert Louis Franch, George Diedrich Gristede, Matthew Mantell Ziegler
  • Publication number: 20170371983
    Abstract: Disclosed is a system, computer program product, and method for performing logic, physical synthesis, and post-route optimization. The method begins with identifying a plurality of groups of paths in a circuit by a unique criteria. The unique criteria is any one of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof. An optimization process is performed on the design and is repeated until the cumulative histogram corresponds to the reference histogram within a threshold. The histogram optimization on the group of paths to make the cumulative histogram correspond to the reference cumulative histogram can be adjusted to account for timing, power, yield, or a combination thereof. After a first group of paths has been optimized, the process can be repeated for other groups of paths. The histogram optimization performed on each group of paths is merged into overall histogram optimization design.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Robert Louis FRANCH, George Diedrich GRISTEDE, Matthew Mantell ZIEGLER