Patents by Inventor George Dietrich

George Dietrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8416556
    Abstract: A power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: April 9, 2013
    Assignees: Conti Temic Microelectronic GmbH, EPCOS AG
    Inventors: Wilhelm Grimm, Wilhelm Hübscher, Harald Vetter, Gerhard Hiemer, Edmund Schirmer, Hermann Kilian, Hermann Bäumel, George Dietrich
  • Publication number: 20090059467
    Abstract: A power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.
    Type: Application
    Filed: April 25, 2006
    Publication date: March 5, 2009
    Inventors: Wilhelm Grimm, Wilhelm Hubscher, Harald Vetter, Gerhard Hiemer, Edmund Schirmer, Hermann Kilian, Hermann Baumel, George Dietrich
  • Publication number: 20060232760
    Abstract: Disclosed is a LADAR system and a method for operating same. The LADAR system includes circuitry for generating the electrical signal with an optical signal detector using N discrete samples; a bank of M parallel sample/hold circuit unit cells individual ones of which operate with an associated sample/hold clock, where each sample/hold clock is shifted in time by a fixed or programmable amount ?t relative to a sample/hold clock of an adjacent sample/hold circuit unit cell; and further includes circuitry for sequentially coupling a sampled value of the electrical signal from a first output of individual ones of at least some of the M parallel sample/hold circuit unit cells to an analog to digital converter circuit. Each of the M parallel sample/hold circuit unit cells has a second output for outputting a digital signal for indicating the state (low or high) during a time that the associated sample/hold clock allowing for time of arrival determination.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 19, 2006
    Inventors: James Asbrock, George Dietrich, Lloyd Linder