Patents by Inventor George Dudnikov, Jr.
George Dudnikov, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11765827Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.Type: GrantFiled: May 26, 2020Date of Patent: September 19, 2023Assignee: Sanmina CorporationInventors: Shinichi Iketani, Dale Kersten, George Dudnikov, Jr.
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Publication number: 20200383204Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.Type: ApplicationFiled: May 26, 2020Publication date: December 3, 2020Inventors: Shinichi Iketani, Dale Kersten, George Dudnikov, JR.
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Patent number: 10667390Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.Type: GrantFiled: October 2, 2017Date of Patent: May 26, 2020Assignee: SANMINA CORPORATIONInventors: Shinichi Iketani, Dale Kersten, George Dudnikov, Jr.
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Publication number: 20180098426Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.Type: ApplicationFiled: October 2, 2017Publication date: April 5, 2018Inventors: Shinichi Iketani, Dale Kersten, George Dudnikov, JR.
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Patent number: 9900978Abstract: Embodiments of the present application relate to the technical field of a printed circuit plate, in particular, to a printed circuit plate and a method manufacturing same so as to resolve a problem of an incomplete elimination of a short-line effect. The method for manufacturing a printed circuit board in the embodiments of the present application comprises a step of drilling target prepregs at positions corresponding to at least one preset hole therein so as to form through holes perforating through the target prepregs, wherein the formed through holes have an aperture greater than that of the preset hole, and the preset hole does not need to transmit electrical signal between layers of the PCB.Type: GrantFiled: October 29, 2012Date of Patent: February 20, 2018Assignees: Peking University Founder Group Co., Ltd., Zhuhai Founder PCB Development Co., Ltd., Chongqing Founder Hi-Tech Electronic Inc.Inventors: Xinhong Su, George Dudnikov, Jr., Shuhan Shi
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Patent number: 9781830Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.Type: GrantFiled: March 11, 2014Date of Patent: October 3, 2017Assignee: Sanmina CorporationInventors: Shinichi Iketani, Dale Kersten, George Dudnikov, Jr.
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Publication number: 20140251663Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.Type: ApplicationFiled: March 11, 2014Publication date: September 11, 2014Applicant: Sanmina CorporationInventors: Shinichi Iketani, Dale Kersten, George Dudnikov, Jr.
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Publication number: 20140190733Abstract: Embodiments of the present application relate to the technical field of a printed circuit plate, in particular, to a printed circuit plate and a method manufacturing same so as to resolve a problem of an incomplete elimination of a short-line effect. The method for manufacturing a printed circuit board in the embodiments of the present application comprises a step of drilling target prepregs at positions corresponding to at least one preset hole therein so as to form through holes perforating through the target prepregs, wherein the formed through holes have an aperture greater than that of the preset hole, and the preset hole does not need to transmit electrical signal between layers of the PCB.Type: ApplicationFiled: October 29, 2012Publication date: July 10, 2014Applicants: PEKING UNIVERSITY FOUNDER GROUP CO., LTD., ZHUHAI FOUNDER PCB DEVELOPMENT CO., LTD., CHONGQING FOUNDER HI-TECH ELECTRONIC INC.Inventors: George Dudnikov, JR., Xinhong Su, Shuhan Shi
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Patent number: 8667675Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: GrantFiled: August 12, 2008Date of Patent: March 11, 2014Assignee: Sanmina Sci CorporationInventor: George Dudnikov, Jr.
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Patent number: 8222537Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: GrantFiled: June 11, 2009Date of Patent: July 17, 2012Assignee: Sanmina-Sci CorporationInventors: George Dudnikov, Jr., Franz Gisin
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Patent number: 8156640Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.Type: GrantFiled: October 4, 2008Date of Patent: April 17, 2012Assignee: Sanmina-SCI CorporationInventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
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Patent number: 7688598Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.Type: GrantFiled: February 16, 2006Date of Patent: March 30, 2010Assignee: Sanmina-SCI CorporationInventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
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Publication number: 20090288874Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: ApplicationFiled: June 11, 2009Publication date: November 26, 2009Applicant: SANMINA SCI CORPORATIONInventors: George Dudnikov, JR., Franz Gisin
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Patent number: 7593203Abstract: Protection for sensitive components on a printed circuit board by selectively depositing transient protection material on one or more layers of the printed circuit board is disclosed.Type: GrantFiled: February 16, 2006Date of Patent: September 22, 2009Assignee: Sanmina-SCI CorporationInventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
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Publication number: 20090025213Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.Type: ApplicationFiled: October 4, 2008Publication date: January 29, 2009Applicant: SANMINA SCI CORPORATIONInventors: George Dudnikov, JR., Franz Gisin, Gregory J. Schroeder
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Publication number: 20080301934Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: ApplicationFiled: August 12, 2008Publication date: December 11, 2008Applicant: SANMINA SCI CORPORATIONInventor: George Dudnikov, JR.
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Publication number: 20080296057Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: ApplicationFiled: August 12, 2008Publication date: December 4, 2008Applicant: SANMINA SCI CORPORATIONInventor: George Dudnikov, JR.