Patents by Inventor George E. Barbera

George E. Barbera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7836365
    Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: November 16, 2010
    Assignee: Broadcom Corporation
    Inventors: George E. Barbera, David C. Crohn
  • Patent number: 6968488
    Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 22, 2005
    Assignee: Broadcom Corporation
    Inventors: George E. Barbera, David C. Crohn
  • Publication number: 20030167430
    Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.
    Type: Application
    Filed: June 28, 2002
    Publication date: September 4, 2003
    Inventors: George E. Barbera, David C. Crohn
  • Patent number: 5155383
    Abstract: A master/slave flipflop uses a reset circuit to initialize its output to a known state. A data input signal and a reference signal are received at first and second inputs of a differential transistor input stage respectively for developing first and second output signals having opposite logic states at first and second nodes. A locking circuit locks the logic states of the first and second output signals at the first and second nodes respectively. A reset circuit reduces the second output signal at the second node upon receiving a reset signal to establish a logic low state at the second node and a logic high state at the first node which transfer through the slave portion as the output signals of the flipflop circuit.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: October 13, 1992
    Assignee: Motorola, Inc.
    Inventor: George E. Barbera