Patents by Inventor George E. Georgiou

George E. Georgiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090015239
    Abstract: A system and method in which an overhead high voltage transmission line sensor system is able to measure one or more of temperature, current, and line sag for a conductor within a high voltage transmission line system. The sensor system may be able to clamp to a transmission conductor or splice, harvest power from the transmission line, and/or transmit data corresponding to measurements of current, temperature, and line sag.
    Type: Application
    Filed: March 3, 2008
    Publication date: January 15, 2009
    Inventors: George E. Georgiou, Ken K. Chin, Raymond Ferraro, Guanhua Feng, Karen Gail Noe
  • Patent number: 5977830
    Abstract: A low noise transistor IC or module comprises a plurality of conventional CMOS transistors which are laid out in parallel in such a way that the effective gate width of the combination of transistors is increased, yet the effective gate resistance and hence the noise figure (NF) of the circuit are reduced. A low noise amplifier incorporating such a module is also described.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: November 2, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Young-Kai Chen, George E. Georgiou
  • Patent number: 5851922
    Abstract: The invention is directed to a process for forming p.sup.+ and n.sup.+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected to a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is performed after the n-type dopant is implanted into the structure. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n.sup.+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: December 22, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Joze Bevk, Matthias Werner Fuertsch, George E. Georgiou, Steven James Hillenius
  • Patent number: 4692349
    Abstract: Selective electroless plating of cobalt or nickel is utilized to form conductive plugs in high-aspect-ratio vias in VLSI devices. Particularly good results are obtained when an active or catalytic film is formed on the via bottoms to serve as a plating base.
    Type: Grant
    Filed: March 3, 1986
    Date of Patent: September 8, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: George E. Georgiou, Gary N. Poli
  • Patent number: 4618972
    Abstract: An improved X-ray source for a lithographic system comprises a double-angle conical target. The target is characterized by a small apparent source diameter and an efficient cooling system. Submicron resolution and high-power operation are thereby made feasible.
    Type: Grant
    Filed: September 7, 1984
    Date of Patent: October 21, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: George E. Georgiou, Martin E. Poulsen