Abstract: The invention is a system and method for high-efficiency checkerboard memory self-test. A random pattern generator configuration includes a linear feedback shift register and a multiple input signature register. The random pattern generator is used to step through the memory addresses in generating the checkerboard pattern. The two least significant address lines connecting the random pattern generator and the memory array are connected together via an exclusive OR gate. Because these address lines indicate the parity of the current and next memory addresses to be generated in the random pattern generator, the output of the exclusive OR gate indicates whether the next memory address to be generated is of the same or different type of state compared to the current memory address. The output of the exclusive OR gate can thus be connected to the data input shift register of the memory array to permit conditional shifting of the checkerboard data pattern into the memory array.

Abstract: A system and method for on-chip self test of memory circuits is disclosed. Memory circuit testing is accomplished by using a random pattern generator based upon a primitive polynomial and including a linear feedback shift register having at least one stage in addition to the number of address lines required for addressing the memory. The random pattern generator is capable of cycling through all memory addresses, including the all zero address. During each of four random pattern generator cycles, known data is written in or read out of each memory cell. By including means for writing and reading the complement of data during different random pattern generator cycles, both possible states of each memory cell may be tested. The outputted data is routed to multiple input signature register which generates a data signature for the memory which can in turn be compared to that known for a good memory.