Abstract: A thin film FET switching element, particularly useful in liquid crystal displays, employs a set of special materials to ensure compatibility with the indium tin oxide of a pixel electrode layer used as transparent conductive material in liquid crystal display devices. These materials include the use of titanium as a gate electrode material and the use of aluminum as a material to enhance electrical contact between source and drain pads and an underlying layer of amorphous silicon. The apparatus and process of the present invention provide enhanced fabrication yield and device reliability.

Abstract: A process for the fabrication of thin film field effect transistors in active matrix liquid crystal display devices includes the utilization of a protective, conductive tab disposed on a corner portion of the pixel electrodes. Electrical contact is made to the pixel electrodes not directly, but rather through a via opening in protective, insulative and amorphous silicon layers. The structure is particularly advantageous in that it permits the utilization of a wider range of gate and upper level metallization materials, particularly aluminum, whose etchants are otherwise found deleterious to pixel electrode material such as indium tin oxide. The structure of the present invention is seen to be readily fabricatable in accordance with high yield fabrication procedures.

Abstract: Electrical contact to doped amorphous silicon material is enhanced by depositing a thin layer of molybdenum on the amorphous silicon surface and subsequently removing it. This treatment is found to permanently alter the silicon surface so as to facilitate and improve electrical contact to the silicon material by subsequently deposited metallization layers for source and drain electrode attachment. The layer of molybdenum which is deposited and removed need only be approximately 50 nanometers in thickness to produce desirable results. The method is particularly useful in the fabrication of thin film, inverted, amorphous silicon field effect transistors. Furthermore, such devices are particularly useful in the fabrication of liquid crystal display systems employing such field effect transistors in matrix addressed arrays used for switching individually selected pixel elements.

Abstract: An organic or inorganic base solution is employed as a means for passivating the back channel region of an amorphous silicon FET device following plasma etching of the back channel region. The passivation provided significantly reduces back channel leakage currents resulting in FET devices which are compatible with conventional processing methods and which exhibit desirable properties for use in liquid crystal display systems.

Abstract: An amorphous silicon thin film FET is doped and structured to be particularly useful for use in liquid crystal display circuits. In particular, critical FET dimensions are provided along with doping levels and locations which permit optimal reduction of source to gate capacitance, while at the same time, preventing the occurrence of large contact voltage drops. Critical dimensions include active channel length, source-gate overlap, and amorphous silicon thickness. A critical relationship is established amongst these parameters and amorphous silicon doping levels.

Abstract: An amorphous silicon thin film FET is structured to be particularly useful for use in liquid crystal display circuits. In particular, critical FET dimensions are provided which permit optimal reduction of source to gate capacitance, while at the same time, preventing the occurrence of large contact voltage drops. Critical dimensions include active channel length, source-gate overlap, and amorphous silicon thickness. A critical relationship is established amongst these parameters.

Abstract: The gate electrode in an inverted field effect transistor (FET) is fabricated with titanium to provide an FET which is particularly suitable for use as the switching element in a matrix addressed liquid crystal display. More particularly, the resist employed in gate electrode patterning is plasma ashed in an oxygen atmosphere to toughen the titanium gate material and render it more amenable to subsequent processing steps.

Abstract: A beam-addressed memory system for digital memory recording and reading which comprises an electron beam generating and focusing subsystem, an electron detecting subsystem, electronic control and interface circuit means, and a storage medium consisting essentially of a cross-linkable polymeric film having an implanted surface layer of heavy metal ions.

Abstract: An improved target for storage of electric charge, in an electron beam addressable memory, utilizes an anodic oxide grown upon a semiconductor layer, forming part of a semiconductor diode structure. The anodic oxide is overlayed with a planar film of conductive material and the target structure is scanned with an electron beam for writing of electric charge storage therein and reading of the electron charge patterns therefrom over relatively greater numbers of erase/write operations relative to a target having a thermally-grown oxide layer.

Abstract: The amount of charge written into the insulator layer of an electron-beam-addressed metal-insulator-semiconductor target is increased by increasing the number of defects in the insulator to provide additional charge trapping and storage sites. Ion implantation techniques for accomplishing the increase of charge trapping sites are disclosed.

Abstract: Binary information is stored in a semiconductor archival memory medium by formation of a region of an alloy, of the semiconductor material and a non-doping material, at each of a plurality of potential memory sites at which a first binary value of information is to be stored, with the remaining data sites being devoid of the alloyed region to store the remaining value of binary data. Methods for writing the formation of the alloyed region, and reading the information value stored at each memory site, are also disclosed.

Abstract: A method for storing data in an archival memory semiconductor target by inducing damage to the semiconductor lattice at selected ones of a plurality of storage sites arranged as a two-dimensional array upon a surface of the target. Ions are accelerated and collimated as a beam to impinge upon a target surface to induce the damage to a controlled depth, whereby subsequent illumination of a damaged data site by an electron beam will allow the beam-produced electron-hole pairs to recombine within the damaged area to prevent increased current flow and read a binary zero bit, while hole migrations through a target depletion region will cause increased current flow, at an undamaged data site, to indicate a binary one data bit.

Abstract: A method for randomly scrambling the physical address of a block of data, within a memory subject to data site deterioration, by utilizing an auxiliary correspondence memory to pair each logical input/output address with a physical memory address at a random time. Apparatus for implementing the novel method is also disclosed.

Abstract: A non-volatile archival memory storage media has a planar junction diode structure into which are written a plurality of diode bits permanently formed at or beneath the top surface thereof by selective ion implantation. Each of the plurality of ion implanted regions represents a data bit of a first binary value, with the remaining un-implanted regions of the planar diode representing data bits of the remaining binary value. The permanently stored data is read by inducing a flow of current by recombination phenomena responsive to a scanning electron beam sequentially incident on each of the possible data bit sites of an array of such sites in the planar diode. Wide bandwidth methods for writing the ion implantation sites into the planar diode media are disclosed.