Abstract: The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline.

Abstract: The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline.

Abstract: A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.