Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.

Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: A method and apparatus for generating a voltage that is proportional to an absolute temperature (PTAT voltage). A current generator for generating a current that is proportional to absolute temperature (PTAT current) has an internal resistance and two diodes. The PTAT current is proportional to the resistance, and the temperature coefficient of the PTAT current is defined by the ratio of diode current densities. A feedback circuit has a source follower that is connected to the current generator for driving the output node with a regulated PTAT current wherein the PTAT current is mirrored accurately, providing a constant Vref.

Abstract: A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal.

Abstract: A system to improve a voltage-controlled oscillator may include a voltage-controlled oscillator. The system may also include a switch to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain.

Abstract: In temperature sensing circuitry PTAT (Proportional to Absolute Temperature) Voltage References are typically used. By adding a feedback circuit and a source follower into the classic design, the circuit can guarantee that the current is mirrored identically regardless of the value of power supply voltage. This added circuitry is easy to implement and is low in both power and area. The essence of this invention is that the PTAT circuit allows a large range of operation including low voltage (1 Volt) and more accurate temperature readings.

Abstract: An electrically blowable fuse circuit having a fuse which may be placed in a condition to be blown. The circuit includes a first transistor having a body, a source, a drain, and a gate. The source is connected to one end of the fuse and the drain is connected to ground. The first transistor further includes a controllable parasitic device in its body. A second transistor is connected to the parasitic device such that when the second transistor is turned on, the parasitic device turns on the first transistor, allowing the fuse to be blown when the fuse is placed in a condition to be blown.

Abstract: A state detection circuit for a fusible element includes a differential sensing circuit that compares voltage at a detection point in a path containing the fusible element with that at a reference point in a path establishing a non-zero reference voltage. The paths are similarly configured except one contains the fusible element while the other contains a device establishing the reference voltage. The two paths in any given sensing circuit are located in close proximity to each other so that even though element parameters in the paths of different sensing circuits may vary significantly, those values track each other in the given sensing circuit. As a result, the normal non-zero value of the voltage at the reference point maintains a relationship to that at the detection point that enables the differential sensing circuit to detect between a fused and an unfused element irrespective of variation in circuit element parameters.

Abstract: A first or primary field effect transistor (“FET”) is separated from a body contact thereto by one or more second FETs that are placed electrically in parallel with the first FET. In this way, the body of the first FET can be extended into the region occupied by the second FET to allow contact to be made to the body of the first FET. In one embodiment, the gate conductor of the first FET and a gate conductor of the second FET are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.

Abstract: A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers.

Abstract: An identification circuit for establishing and sensing the state of a fusible element used in on chip identification of the chip's type comprising: a circuit establishing control signals for turning the identification circuit on and off; dual paths energized by the control signals generated by the level setting circuit to energize one path through the fusible element to provide a state level and the other path through a reference path which provides a reference voltage level which is distinguishable from both the blown and unblown states of the fusible element; a differential sensing circuit for comparing the reference voltage level to the state level to provide a signal indicating the state of the fusible element; and protection circuitry to protect the circuit during an operation in which the state of the fusible element is set.

Abstract: Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.

Abstract: Disclosed is a type “BC” body contacted SOI transistor and process for making these transistors in a manufacturing environment by providing a structure and process which removes overlay tolerance from the effective transistor width. The width is determined by RX on the top side, but by PC on the other with source and drain connected together. In the preferred embodiment such a structure is used as the top part of the SOI transistor with the bottom part a mirror image of the top part such that the effect of the PC to RX overlay is reversed, and the top part and bottom part are connected by a common body part. For the bottom part an “UP misalignment will make the device with large, while a “DOWN” misalignment will make the device width smaller. Thus, if PC is misalleged with respect to RX, any width errors introduced in the top part of the transistor will be exactly canceled by the bottom part of the transistor.

Abstract: A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

Abstract: A self-aligned SOI FET device with an "L" shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a "T" shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.

Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.

Abstract: A current switch emitter-follower logic circuit allows both the UP output logic level and the DOWN output logic level to be independently controlled with respect to a fixed reference voltage so as to permit very small output level swings. A feedback circuit generates two different control signals which are independently variable and are input to a control circuit and to a logic circuit to compensate for fluctuations in power supply voltages, temperature and circuit parameters. These control signals are applied to a variable current source within the logic circuit and to a dynamic resistance within the control circuit to compensate almost instantaneously to fluctuations in power supply voltage, temperature or circuit device parameters, maintaining the logic circuit output levels close to reference levels so as to permit small output signal swings. The output logic levels need not be symmetrical around a central reference point.