Patents by Inventor George Edward Curtis
George Edward Curtis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715920Abstract: In one embodiment, an apparatus includes a connector plug for attachment to a single pair Ethernet cable comprising a pair of conductors, and configured for being received in a connector receptacle. The connector plug includes a first end for receiving the single pair Ethernet cable and a second end having a pair of contacts, each of the contacts comprising a receptacle contact interface, a conductor interface, and an extension to provide an increased width between conductor gripping prongs at the conductor interface while maintaining a consistent spacing between the pair of contacts at the receptacle contact interface with connector plugs configured to mate with different gauge cables. The connector plug comprises a latch for secure attachment to the receptacle and a pull cord connected to the latch and accessible when the connector plug is inserted into the receptacle with other connector plugs for release of the connector plug.Type: GrantFiled: April 1, 2021Date of Patent: August 1, 2023Assignee: CISCO TECHNOLOGY, INC.Inventors: George Edward Curtis, Amrik S. Bains, Edward John Kliewer
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Patent number: 11716836Abstract: A chassis-mounted electronic device includes a conductive chassis, an upper EMI gasket, and a lower EMI gasket. An upper chassis and a lower chassis of the conductive chassis are coupled to form an interior of the chassis housing an electronic device. The upper EMI gasket is attached to the upper chassis, and resiliently contacts a portion of the electronic device. The lower EMI gasket is attached to the lower chassis, and resiliently contacts a different portion of the electronic device. The upper and lower EMI gaskets include perforations to allow cooling air through the EMI gaskets and into the interior of the chassis. The conductive chassis, the upper EMI gasket, and the lower EMI gasket provide EMI shielding for the electronic device.Type: GrantFiled: July 7, 2021Date of Patent: August 1, 2023Assignee: CISCO TECHNOLOGY, INC.Inventors: Vic Hong Chia, George Edward Curtis, John David Stallings
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Patent number: 11482802Abstract: An apparatus includes a printed circuit board (PCB). The PCB includes a plurality of through-holes extending through the PCB between a PCB first surface and a PCB second surface that opposes the PCB first surface, where each through-hole includes a via extending from the PCB first surface to a depth within the through-hole that is distanced from the PCB second surface. An integrated circuit surface mount is connected at the PCB first surface with vias of the through-holes, and a cable interconnect assembly is surface mount connected at the PCB second surface. The cable interconnect assembly includes a plurality of contact pins, each contact pin extending within a corresponding through-hole and having a sufficient dimension to engage and electrically connect with the via of the corresponding through-hole so as to facilitate exchange of an electrical signal between the integrated circuit and the cable interconnect assembly.Type: GrantFiled: May 28, 2021Date of Patent: October 25, 2022Assignee: CISCO TECHNOLOGY, INC.Inventors: Jason Visneski, George Edward Curtis, Mike Sapozhnikov, Peter Gunadisastra, Joel Goergen
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Publication number: 20220181807Abstract: An apparatus includes a printed circuit board (PCB). The PCB includes a plurality of through-holes extending through the PCB between a PCB first surface and a PCB second surface that opposes the PCB first surface, where each through-hole includes a via extending from the PCB first surface to a depth within the through-hole that is distanced from the PCB second surface. An integrated circuit surface mount is connected at the PCB first surface with vias of the through-holes, and a cable interconnect assembly is surface mount connected at the PCB second surface. The cable interconnect assembly includes a plurality of contact pins, each contact pin extending within a corresponding through-hole and having a sufficient dimension to engage and electrically connect with the via of the corresponding through-hole so as to facilitate exchange of an electrical signal between the integrated circuit and the cable interconnect assembly.Type: ApplicationFiled: May 28, 2021Publication date: June 9, 2022Inventors: Jason Visneski, George Edward Curtis, Mike Sapozhnikov, Peter Gunadisastra, Joel Goergen
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Patent number: 11201752Abstract: Disclosed herein is a technique for a connection from an Ethernet physical transceiver (PHY) to an integrated connector module (ICM) where the connection and the ICM lack a common mode choke. The ICM can include a magnetic coupler that directly couples an Ethernet jack and the PHY.Type: GrantFiled: December 19, 2016Date of Patent: December 14, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: George Edward Curtis, William Oberlin, Chris Desiniotis, Amrik Singh Bains
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Publication number: 20210337707Abstract: A chassis-mounted electronic device includes a conductive chassis, an upper EMI gasket, and a lower EMI gasket. An upper chassis and a lower chassis of the conductive chassis are coupled to form an interior of the chassis housing an electronic device. The upper EMI gasket is attached to the upper chassis, and resiliently contacts a portion of the electronic device. The lower EMI gasket is attached to the lower chassis, and resiliently contacts a different portion of the electronic device. The upper and lower EMI gaskets include perforations to allow cooling air through the EMI gaskets and into the interior of the chassis. The conductive chassis, the upper EMI gasket, and the lower EMI gasket provide EMI shielding for the electronic device.Type: ApplicationFiled: July 7, 2021Publication date: October 28, 2021Inventors: Vic Hong Chia, George Edward Curtis, John David Stallings
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Patent number: 11140800Abstract: An apparatus suitable for providing ventilation and electromagnetic interference (EMI) containment for a computing device includes a first strip and a second strip. The first strip is sized to span ventilation openings of a computing device covering. The second strip intersects the first strip while also spanning the ventilation openings. Thus, the first strip and the second strip cooperate to define airflow openings within the ventilation openings, the airflow openings being sized to inhibit EMI from exiting the computing device via the ventilation openings.Type: GrantFiled: January 23, 2019Date of Patent: October 5, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: Vic Hong Chia, George Edward Curtis, Adriana del Pilar Rangel, Keith Frank Tharp, Alpesh Umakant Bhobe
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Publication number: 20210298211Abstract: A chassis-mounted electronic device includes a chassis, an upper EMI gasket, and a lower EMI gasket is provided. The chassis, including an upper chassis and a lower chassis, is constructed from a conductive sheet with a first thickness. The upper chassis and the lower chassis are coupled to form an interior of the chassis housing an electronic device. The upper EMI gasket is attached to the upper chassis, and is thinner than the upper chassis. The lower EMI gasket is attached to the lower chassis, and is also thinner than the lower chassis. The upper and lower EMI gaskets include perforations to allow cooling air through the EMI gaskets and into the interior of the chassis. Both the upper EMI gasket and the lower EMI gasket are configured to resiliently contact a portion of the electronic device to provide EMI shielding for the electronic device.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Inventors: Vic Hong Chia, George Edward Curtis, John David Stallings
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Patent number: 11129311Abstract: A chassis-mounted electronic device includes a chassis, an upper EMI gasket, and a lower EMI gasket is provided. The chassis, including an upper chassis and a lower chassis, is constructed from a conductive sheet with a first thickness. The upper chassis and the lower chassis are coupled to form an interior of the chassis housing an electronic device. The upper EMI gasket is attached to the upper chassis, and is thinner than the upper chassis. The lower EMI gasket is attached to the lower chassis, and is also thinner than the lower chassis. The upper and lower EMI gaskets include perforations to allow cooling air through the EMI gaskets and into the interior of the chassis. Both the upper EMI gasket and the lower EMI gasket are configured to resiliently contact a portion of the electronic device to provide EMI shielding for the electronic device.Type: GrantFiled: March 23, 2020Date of Patent: September 21, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: Vic Hong Chia, George Edward Curtis, John David Stallings
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Publication number: 20210218202Abstract: In one embodiment, an apparatus includes a connector plug for attachment to a single pair Ethernet cable comprising a pair of conductors, and configured for being received in a connector receptacle. The connector plug includes a first end for receiving the single pair Ethernet cable and a second end having a pair of contacts, each of the contacts comprising a receptacle contact interface, a conductor interface, and an extension to provide an increased width between conductor gripping prongs at the conductor interface while maintaining a consistent spacing between the pair of contacts at the receptacle contact interface with connector plugs configured to mate with different gauge cables. The connector plug comprises a latch for secure attachment to the receptacle and a pull cord connected to the latch and accessible when the connector plug is inserted into the receptacle with other connector plugs for release of the connector plug.Type: ApplicationFiled: April 1, 2021Publication date: July 15, 2021Applicant: CISCO TECHNOLOGY, INC.Inventors: George Edward Curtis, Amrik S. Bains, Edward John Kliewer
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Patent number: 10998685Abstract: In one embodiment, an apparatus includes a connector plug for attachment to a single pair Ethernet cable comprising a pair of conductors, and configured for being received in a connector receptacle. The connector plug includes a first end for receiving the single pair Ethernet cable and a second end having a pair of contacts, each of the contacts comprising a receptacle contact interface, a conductor interface, and an extension to provide an increased width between conductor gripping prongs at the conductor interface while maintaining a consistent spacing between the pair of contacts at the receptacle contact interface with connector plugs configured to mate with different gauge cables.Type: GrantFiled: November 8, 2018Date of Patent: May 4, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: George Edward Curtis, Amrik S. Bains, Edward John Kliewer
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Publication number: 20200236825Abstract: An apparatus suitable for providing ventilation and electromagnetic interference (EMI) containment for a computing device includes a first strip and a second strip. The first strip is sized to span ventilation openings of a computing device covering. The second strip intersects the first strip while also spanning the ventilation openings. Thus, the first strip and the second strip cooperate to define airflow openings within the ventilation openings, the airflow openings being sized to inhibit EMI from exiting the computing device via the ventilation openings.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Inventors: Vic Hong Chia, George Edward Curtis, Adriana del Pilar Rangel, Keith Frank Tharp, Alpesh Umakant Bhobe
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Publication number: 20200153174Abstract: In one embodiment, an apparatus includes a connector plug for attachment to a single pair Ethernet cable comprising a pair of conductors, and configured for being received in a connector receptacle. The connector plug includes a first end for receiving the single pair Ethernet cable and a second end having a pair of contacts, each of the contacts comprising a receptacle contact interface, a conductor interface, and an extension to provide an increased width between conductor gripping prongs at the conductor interface while maintaining a consistent spacing between the pair of contacts at the receptacle contact interface with connector plugs configured to mate with different gauge cables.Type: ApplicationFiled: November 8, 2018Publication date: May 14, 2020Applicant: CISCO TECHNOLOGY, INC.Inventors: George Edward Curtis, Amrik S. Bains, Edward John Kliewer
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Publication number: 20200059021Abstract: In one embodiment, an eye of needle (EON) press-fit pin includes a base, a tip, and a compliant portion extending longitudinally between the base and the tip and comprising a pair of resilient deformable arms joined at opposite ends and defining an opening therebetween. The arms each include an outer surface for at least partial engagement with walls of an electrical via upon insertion therein. The outer surface of each of the arms includes a central segment having a flat longitudinal surface and converges from the central segment towards the base and the tip. The arms each further include an inner surface defining the opening and forming an elongated portion at each end of the opening for stress relief.Type: ApplicationFiled: August 20, 2018Publication date: February 20, 2020Applicant: CISCO TECHNOLOGY, INC.Inventors: Qirong Lin, George Edward Curtis, Ki-Yuen Chau, Quan Lu, Xiaogang Li
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Patent number: 10547128Abstract: In one embodiment, an eye of needle (EON) press-fit pin includes a base, a tip, and a compliant portion extending longitudinally between the base and the tip and comprising a pair of resilient deformable arms joined at opposite ends and defining an opening therebetween. The arms each include an outer surface for at least partial engagement with walls of an electrical via upon insertion therein. The outer surface of each of the arms includes a central segment having a flat longitudinal surface and converges from the central segment towards the base and the tip. The arms each further include an inner surface defining the opening and forming an elongated portion at each end of the opening for stress relief.Type: GrantFiled: August 20, 2018Date of Patent: January 28, 2020Assignee: CISCO TECHNOLOGY, INC.Inventors: Qirong Lin, George Edward Curtis, Ki-Yuen Chau, Quan Lu, Xiaogang Li
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Patent number: 10522280Abstract: The subject disclosure relates to improved integrated connector module (ICM) designs for Ethernet applications. Some aspects provide an improved integrated connector module transformer (ICMt), including a wafer configured to hold a plurality of toroid elements, wherein the wafer is comprised of two or more mechanically coupled wafer portions. The ICMt can include one or more Electro Magnetic Interference (EMI) fingers that are configured to contact a ground pad of a printed circuit board (PCB) in order to provide a low-inductance connection between the ICMt and the ground pad of the PCB.Type: GrantFiled: January 17, 2017Date of Patent: December 31, 2019Assignee: CISCO TECHNOLOGY, INC.Inventors: William F. Edwards, George Edward Curtis, Ki Yuen Chau, Sandeep Arvindkumar Patel, Keith Frank Tharp, Robin Carol Johnson, Yu Liu, Billie Alton Hudson
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Patent number: 10431914Abstract: A network connector assembly with an upper board member includes one or more upper coupling pins and a lower board member includes one or more lower coupling pins. The upper board member and lower board member each a plurality of sets of contact pins disposed on a respective top surface. A housing can be disposable over the upper board member and the lower board member forming one or more network couplers. Each of the one or more network couplers configured to receive one set of contact pins.Type: GrantFiled: July 27, 2017Date of Patent: October 1, 2019Assignee: CISCO TECHNOLOGY, INC.Inventors: George Edward Curtis, Amrik S. Bains, Ken Naumann, Mike Sapozhnikov
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Publication number: 20190036252Abstract: A network connector assembly with an upper board member includes one or more upper coupling pins and a lower board member includes one or more lower coupling pins. The upper board member and lower board member each a plurality of sets of contact pins disposed on a respective top surface. A housing can be disposable over the upper board member and the lower board member forming one or more network couplers. Each of the one or more network couplers configured to receive one set of contact pins.Type: ApplicationFiled: July 27, 2017Publication date: January 31, 2019Inventors: George Edward Curtis, Amrik S. Bains, Ken Naumann, Mike Sapozhnikov
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Publication number: 20180175675Abstract: Disclosed herein is a technique for a connection from an Ethernet physical transceiver (PHY) to an integrated connector module (ICM) where the connection and the ICM lack a common mode choke. The ICM can include a magnetic coupler that directly couples an Ethernet jack and the PHY.Type: ApplicationFiled: December 19, 2016Publication date: June 21, 2018Inventors: George Edward Curtis, William Oberlin, Chris Desiniotis, Amrik Singh Bains
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Patent number: D807830Type: GrantFiled: February 17, 2016Date of Patent: January 16, 2018Assignee: Cisco Technology, Inc.Inventors: George Edward Curtis, Edward John Kliewer, Amrik Singh Bains