Abstract: A device includes one or more ports, one or more bandwidth shapers, and processing logic. The one or more ports are to connect to a communication network. A given bandwidth shaper is to: (i) when disabled, output traffic at an available full data rate, and (ii) when enabled, output the traffic at a specified shaper data rate lower than the available full data rate. The processing logic is to receive or generate notifications, which are indicative of average power that is consumed by the network device while outputting traffic through the one or more bandwidth shapers via the one or more ports, and based on at least some of the notifications, toggle at least one of the one or more bandwidth shapers between being enabled and disabled, to retain the average power consumed below a specified power budget.

Abstract: An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.

Abstract: An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.

Abstract: A system, device and method are provided for assessing actions of authenticated persons within an enterprise system. The illustrative method includes providing an application for processing a workflow with services a database for each service. The method includes configuring each of the services to write events to respective databases. Each database can have a dedicated outbox table of events for that service. The method includes, with an event platform: configuring a connector for consuming events to process events in the dedicated outbox tables and determining one or more subscription topics associated with the processed events. The method includes, based on the one or more determined subscription topics, generating, and transmitting one or more notifications, and posting transmission of the one or more notifications to another topic, the other topic being associated with the determined one or more topics.

Abstract: An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.

Abstract: A device includes one or more ports, one or more bandwidth shapers, and processing logic. The one or more ports are to connect to a communication network. A given bandwidth shaper is to: (i) when disabled, output traffic at an available full data rate, and (ii) when enabled, output the traffic at a specified shaper data rate lower than the available full data rate. The processing logic is to receive or generate notifications, which are indicative of average power that is consumed by the network device while outputting traffic through the one or more bandwidth shapers via the one or more ports, and based on at least some of the notifications, toggle at least one of the one or more bandwidth shapers between being enabled and disabled, to retain the average power consumed below a specified power budget.

Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

Abstract: A network element includes multiple ports and forwarding circuitry. The ports are configured to serve as network interfaces for exchanging packets with a communication network. The forwarding circuitry is configured to receive a multicast packet that is to be forwarded via a plurality of the ports over a plurality of paths through the communication network to a plurality of destinations, to identify a path having a highest latency among the multiple paths over which the multicast packet is to be forwarded, to forward the multicast packet to one or more of the paths other than the identified path, using a normal scheduling process having a first forwarding latency, and to forward the multicast packet to at least the identified path, using an accelerated scheduling process having a second forwarding latency, smaller than the first forwarding latency.

Abstract: One or more blocks of dynamic random access memory are embedded together with a processor and a data bus on an integrated circuit. The data bus has a bandwidth b for general operation including memory access, the block of dynamic random access memory further requiring data refresh at a refresh rate r. The block thus forms an eDRAM on the integrated circuit, typically an ASIC. A refresh controller embedded with the eDRAM may control refresh by clocking the data bus at a rate higher than the rate of the data bus to accommodate both the required memory access and the required data refresh.

Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.

Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.

Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.

Abstract: Communication apparatus includes multiple ports configured to serve as ingress and egress ports, such that the ingress ports receive packets from a packet data network for forwarding to respective egress ports. The ports include an egress port configured for connection to a network interface controller (NIC) serving multiple physical computing units, which have different, respective destination addresses and are connected to the NIC by different, respective communication channels. Control and queuing logic is configured to queue the packets that are received from the packet data network for forwarding to the multiple physical computing units in different, respective queues according to the destination addresses, and to arbitrate among the queues so as to convey the packets from the queues via the same egress port to the NIC, for distribution to the multiple physical computing units over the respective communication channels.

Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.

Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

Abstract: A network element includes multiple ports and forwarding circuitry. The ports are configured to serve as network interfaces for exchanging packets with a communication network. The forwarding circuitry is configured to receive a multicast packet that is to be forwarded via a plurality of the ports over a plurality of paths through the communication network to a plurality of destinations, to identify a path having a highest latency among the multiple paths over which the multicast packet is to be forwarded, to forward the multicast packet to one or more of the paths other than the identified path, using a normal scheduling process having a first forwarding latency, and to forward the multicast packet to at least the identified path, using an accelerated scheduling process having a second forwarding latency, smaller than the first forwarding latency.