Abstract: An analog electrical signal is converted into a binary digital signal by means of an arrangement of semiconductor surface potential wells. During operation, this arrangement converts the analog electrical signal into an analog signal charge packet in one of these potential wells and sequentially subtracts from this analog packet a sequence of reference charge packets representing the binary digital bits of the analog signal, provided that the then remaining signal charge packet is greater than the reference charge packet.

Abstract: In one embodiment, an extremely short channel FET is made by forming a metal layer over a wafer, depositing silicon dioxide over part of the metal layer, oxidizing the exposed metal, controllably etching a portion of the silicon dioxide to expose a small strip of the nonoxidized metal layer, electroplating the exposed metal strip, thereby to form an extremely narrow gate electrode, removing the deposited SiO.sub.2, the metal oxide and the remaining metal layer to leave only the gate electrode, and using the gate electrode as a mask for ion implanting source and drain regions. Since the gate electrode can be made so narrow, the channel region is correspondingly short to give extremely high frequency capabilities. Other embodiments are also described.

Abstract: An extremely short channel Field Effect Transistor (FET) is made by making a first ion implant through a polysilicon mask aperture, converting the surface of the polysilicon into SiO.sub.2 to constrict the aperture size and then making a second ion implant of the opposite type impurity through the constricted aperture. The SiO.sub.2 growth effectively moves the edge of the mask by a small controlled distance. This permits a small controlled spacing between the two ion implants, which is used for defining an extremely short FET channel. Alternatively, a bipolar transistor with a narrow base zone can be made by analogous processing.

Abstract: In one embodiment, an extremely short channel FET is made by forming a metal layer over a wafer, depositing silicon dioxide over part of the metal layer, oxidizing the exposed metal, controllably etching a portion of the silicon dioxide to expose a small strip of the nonoxidized metal layer, electroplating the exposed metal strip, thereby to form an extremely narrow gate electrode, removing the deposited SiO.sub.2, the metal oxide and the remaining metal layer to leave only the gate electrode, and using the gate electrode as a mask for ion implanting source and drain regions. Since the gate electrode can be made so narrow, the channel region is correspondingly short to give extremely high frequency capabilities. Other embodiments are also described.

Abstract: In one embodiment, an extremely short channel FET is made by forming a metal layer over a wafer, depositing silicon dioxide over part of the metal layer, oxidizing the exposed metal, controllably etching a portion of the silicon dioxide to expose a small strip of the nonoxidized metal layer, electroplating the exposed metal strip, thereby to form an extremely narrow gate electrode, removing the deposited SiO.sub.2, the metal oxide and the remaining metal layer to leave only the gate electrode, and using the gate electrode as a mask for ion implanting source and drain regions. Since the gate electrode can be made so narrow, the channel region is correspondingly short to give extremely high frequency capabilities. Other embodiments are also described.