Abstract: A start-up circuit/current source includes a first current path including serially connected first field effect transistor, first resistor, first bipolar transistor, and second resistor. A second current path includes a second field effect transistor, a second bipolar transistor, and a third resistor. The base electrodes of the first and second bipolar transistors are interconnected, and the base and collector of the second bipolar transistor are shorted together. A first current source includes a bipolar transistor serially connected through the third resistor, the base of the third bipolar transistor connected to the first current path. A second current source can be provided including a fourth bipolar transistor serially connected with a fourth resistor and with the base of the fourth transistor connected to a common terminal of the first resistor and first bipolar transistor.

Abstract: An integrated circuit resistor adjustment network with resistors (R1, R2, R3, R4) which may be paralleled by trimming resistors (R5, R7, R6, R8, respectively) upon electrical "zapping" of Zener diodes (Z1, Z2, Z3, Z4, respectively) connected in series with the trimming resistors. The Zener diodes (Z1, Z4 or Z2, Z3) are connected in inverse series via inverse paralleled diodes (D1, D2 or D3, D4 respectively) which are non-conductive during normal operation, but conduct during higher voltage zapping operation to permit the currents for zapping the Zener diodes to bypass the resistors.

Abstract: An arrangement for cancelling the input bias current, at picoampere levels, in linear integrated circuits such as operational amplifiers, comparators, and the like is disclosed herein. This arrangement utilizes circuitry including a tracking transistor which is virtually independent of the presence or absence of leakage current in the overall integrated circuit, even at relatively high temperatures, for example 125.degree. C., where leakage current can be most significant.

Abstract: There is disclosed a dual mode amplifier for use as the output amplifier of a sample and hold circuit. The dual mode amplifier described by the invention is controlled by a sample and hold gate. In one of its modes the characteristics of the amplifier are optimized for best slew rate and transient performance, while in the other mode the amplifier characteristics are optimized for settling time.

Abstract: An integrated circuit including an FET and an analog for cancelling input current that would otherwise be required to supply the FET gate leakage current. The analog establishes a leakage current the magnitude of which is a substantially fixed proportion of the FET leakage current over a given operating range, and employs proportional current mirror means referenced to the analog leakage current to supply the FET leakage current and thereby substantially cancel the input bias current. In a preferred embodiment the analog comprises a lateral PNP multi-collector transistor with one collector connected to its base to establish a reference current, another collector providing the cancellation current, and its base voltage tracking the FET gate voltage so that the two leakage currents remain substantially equal. An analog FET may also be employed to cancel gate-to-drain and gate-to-source leakages. A description of the invention as applied to an operational amplifier is given.

Abstract: An integrated circuit resistor adjustment network with resistors (R1, R.sub.2, R.sub.3, R.sub.4) which may be paralleled by trimming resistors (R5, R7, R6, R8, respectively) upon electrical "zapping" of Zener diodes (Z1, Z2, Z3, Z4, respectively) connected in series with the trimming resistors. The Zener diodes (Z1, Z4 or Z2, Z3) are connected in inverse series via inverse paralleled diodes (D1, D2 or D3, D4 respectively) which are non-conductive during normal operation, but conduct during higher voltage zapping operation to permit the currents for zapping the Zener diodes to bypass the resistors.