Patents by Inventor George Erdos

George Erdos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5293071
    Abstract: A bump structure for bonding leads to a semi-conductor, in which the bump has a thin lower portion which overlaps and seals the edges of the passivation layer, and a thicker upper or stem portion of smaller lateral dimensions to fit within the margins of the opening in the passivation layer. Thus, during bonding, downward compressive forces are applied primarily through the bump stem directly to the metal termination pad beneath the bump, and very little force is applied to the edges of the passivation layer. This reduces the likelihood of passivation layer cracking, increasing device reliability. Because the bump stem is formed within the margins of the passivation layer opening, it has a flat top, resulting in better lead bonding.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: March 8, 1994
    Assignee: Gennum Corporation
    Inventor: George Erdos
  • Patent number: 4953007
    Abstract: A plastic encapsulated integrated circuit package in which a chip is secured to the upper surface of a base and is connected to leads which have their lower surfaces in a plane above that of the bottom of the base. An electrostatic shield is electrically connected to the bottom of the base and underlies the leads without touching them, to reduce crosstalk. The support for the base is integrally connected by a conductive strip to the lead for the ground pin of the chip, to ground the shield. The whole is plastic encapsulated. To permit encapsulation, the shield extends towards but stops short of the dam bars for the leads.
    Type: Grant
    Filed: October 21, 1988
    Date of Patent: August 28, 1990
    Assignee: Linear Technology Inc.
    Inventor: George Erdos