Abstract: The present invention provides a novel direct digital synthesis system architecture which employs a numerically-controlled oscillator (NCO), some decoding logic, and a sine-weighted digital-to-analog converter (DAC) with significantly fewer output values required than conventional DDS systems to provide improved spurious performance (relative to the number of bits of resolution required of the DAC), extended frequency of operation, reduced chip area, and reduced power consumption relative to conventional DDS techniques. The output of the decoder is input to a sine-weighted digital-to-analog converter (DAC). Importantly, the sine-weighted DAC outputs a constant number of samples per cycle using a relatively few number of taps. Although there are significantly fewer taps in the sine-weighted DAC as compared to the linear DAC in conventional DDS systems, each tap of the sine-weighted DAC has a high degree of accuracy, e.g., 16-18 bits.

Abstract: A/D converter or as a D/A converter forms a data converter embedded in a digital circuit for reconfigurable use. Conversion parameters of the data converter are controlled on a bitwise basis from a bitwise converter configuration register. For instance, output locations (i.e., time slots) of the data converter are determined by a bitwise converter configuration register, as is the selection of a D/A conversion mode or A/D conversion mode of the data converter for that particular output location, and/or the output sample length are controlled by appropriate signals from the bitwise converter configuration register. The bitwise converter configuration register also preferably configures the input source to the data converter and/or to an interface, e.g., to a parallel-to-serial, serial-to-serial, or parallel-to-parallel interface device, on a bitwise basis, to provide flexibility both in the source of the channels as well as the output location of particular channels in the data frame.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.

Abstract: There is disclosed an integrated circuit that includes a digital-to-analog converter having a resistor string driven by a current source. The resistor string is coupled to the current source. Intermediate taps are defined at the resistor junctions as well the resistor-current source junctions. Switching transistors are coupled between an output node and a respective intermediate tap. A selection circuit is coupled to a terminal of each switching transistor for selectively switching the transistors to a predetermined state to electrically couple the associated intermediate tap to the output node.

Abstract: There is disclosed an integrated circuit including a resistive material runner resistor string comprising a series of resistors in which each resistor includes at least one runner direction change feature. Each resistor includes first and second contiguous elements. The junction of the first and second elements form a direction change feature such as a corner in the runner of the resistor string. Taps are positioned along the resistor string at substantially equal resistance intervals. The first and second elements may be squares of different edge dimensions. The resistor string is useful in applications such as digital-to-analog converters.

Abstract: A circuit for conversion of an analog input signal to a digital representation of the analog signal. The circuit is typically employed in flash technology, since it is able to produce the digital representation of the analog signal faster and more efficiently than conventional flash converters. The circuit includes a plurality of resistors serially coupled between two reference voltages to form a plurality of nodes therebetween. A plurality of comparators, each having a first input coupled to one of the plurality of nodes and a second input coupled to the analog input signal. Accordingly each comparator compares the analog input signal to a voltage potential at one of the nodes to generate first and second complementary output signals at the outputs of the comparators. The complementary outputs are then applied to a decode circuit having a plurality of digital output lines and switches directly coupled to the digital output lines.

Abstract: An integrated circuit having an analog-to-digital converter includes built-in self-test (BIST) circuitry. The BIST circuitry checks for monotonicity, and typically also that all possible codes are present, by applying a ramp voltage to the A/D input, while a state machine monitors the output. The state machine can check to ensure that the output increases by only one least significant bit (LSB) each time the output changes. A counter may be checked at the end of the test, to ensure that all the possible codes are obtained. The BIST circuitry may be activated, and the results monitored, through package terminals after the chip is packaged, thereby allowing for boundary scan testing. The inventive technique may be used to save testing costs during manufacture. In addition, system diagnostics in the field can become more cost effective.