Patents by Inventor George F. Raiser

George F. Raiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Partial underfill for flip-chip electronic packages
    Patent number: 6700209
    Abstract: An integrated circuit package that contains an underfill material between an integrated circuit and a substrate. The integrated circuit may be mounted to the substrate with solder bumps in a C4 process. The underfill material may extend from an edge of the integrated circuit a length that is no less than approximately 25% of the length between the integrated circuit edge and the integrated circuit center. It has been discovered that a length greater than approximately 25% does not provide a significant reduction in the strain of the solder bumps.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: March 2, 2004
    Assignee: Intel Corporation
    Inventors: George F. Raiser, Bob Sundahl, Ravi Mahajan
  • Partial underfill for flip-chip electronic packages
    Patent number: 6365441
    Abstract: An integrated circuit package that contains an underfill material between an integrated circuit and a substrate. The integrated circuit may be mounted to the substrate with solder bumps in a C4 process. The underfill material may extend from an edge of the integrated circuit a length that is no less than approximately 25% of the length between the integrated circuit edge and the integrated circuit center. It has been discovered that a length greater than approximately 25% does not provide a significant reduction in the strain of the solder bumps.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: George F. Raiser, Bob Sundahl, Ravi Mahajan
  • Semiconductor package
    Patent number: 6049124
    Abstract: A semiconductor package which includes a package substrate and a semiconductor chip located on the package substrate have coefficients of thermal expansion which differs by a large margin. The semiconductor chip has beveled edges and an epoxy is provided which reduce stresses on the semiconductor chip when the package is being heated.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: April 11, 2000
    Assignee: Intel Corporation
    Inventors: George F. Raiser, Gregory Turturro
  • C4 package die backside coating
    Patent number: 5936304
    Abstract: According to one aspect of the invention there is provided a semiconductor chip comprising a semiconductor die, an array of electrical contacts on an integrated circuit in a frontside of the die, and a protective layer on a backside of the die.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: August 10, 1999
    Assignee: Intel Corporation
    Inventors: Mirng-Ji Lii, George F. Raiser, Ravi V. Mahajan, Brad Menzies